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VHDL VHDL Structural Modeling

VHDL VHDL Structural Modeling. Digital Logic. Outline. Structural VHDL Use of hierarchy Component instantiation statements Concurrent statements Test Benches. A general VHDL design. entity entity-name is [ port ( In_1, In_2, In_3 : in bit ;

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VHDL VHDL Structural Modeling

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  1. VHDL VHDL Structural Modeling Digital Logic

  2. Outline • Structural VHDL • Use of hierarchy • Component instantiation statements • Concurrent statements • Test Benches

  3. A general VHDL design entityentity-name is [port ( In_1, In_2, In_3 : in bit; out_1, out_2 : out bit; inout_1, inout_2 : inout bit);] end [entity] [entity-name]; architecture arch-name of entity-name is [declaration] begin architecture body end [architecture] [arch-name];

  4. Component and Signal Declarations • DECLARATION of architecture contains: • component declaration • signal declaration • Example of component declaration componentAND2_OP port(A, B : in bit; Z : out bit); end component; • Example of signal declaration • signallist-of-signal-names:type-name [ := initial-value] ; • ex) signal sig_a, sig_b:bit ;

  5. Concurrent Assignment entityfulladder_dfis port ( A, B, Cin : in bit; Sum, Cout : out bit); end fulladder_df; architecturedata_flowoffulladder_dfis begin Sum <=AxorB xor Cin; Cout <= (AandB) or (AandCin) or (BandCin); enddata_flow;

  6. entityfulladder_bhis port ( A, B, Cin : in bit; Sum, Cout : out bit); end fulladder_bh; architecturebehavioraloffulladder_bhis begin process (A , B, Cin) begin if ( A = ‘0’ and B = ‘0’ and Cin = ‘0’) then Sum <= ‘0’; Cout <= ‘0’; elsif ( A = ‘0’ and B = ‘0’ and Cin = ‘1’) then Sum <= ‘1’; Cout <= ‘0’; elsif ( A = ‘0’ and B = ‘1’ and Cin = ‘0’) then Sum <= ‘1’; Cout <= ‘0’; elsif ( A = ‘0’ and B = ‘1’ and Cin = ‘1’) then Sum <= ‘0’; Cout <= ‘1’; elsif ( A = ‘1’ and B = ‘0’ and Cin = ‘0’) then Sum <= ‘1’; Cout <= ‘0’; elsif ( A = ‘1’ and B = ‘0’ and Cin = ‘1’) then Sum <= ‘0’; Cout <= ‘1’; elsif ( A = ‘1’ and B = ‘1’ and Cin = ‘0’) then Sum <= ‘0’; Cout <= ‘1’; else Sum <= ‘1’; Cout <= ‘1’; end if; end process; endbehavioral; Process

  7. Component Instantiation Statements • The statement part of an architecture body of a structural VHDL description contains component instantiation statements • FORMAT • label :component_name port map (positional association of ports); • label : component_name port map (named association of ports); • EXAMPLES • A1 : AND2_OPport map (A_IN, B_IN, INT1); • A2 : AND2_OPport map (A => A_IN, C => C_IN, Z => INT2);

  8. entityfulladder_stis port ( A, B, Cin : in bit; Sum, Cout : out bit); end fulladder_st; architecturestructraloffulladder_stis componenet XOR3_OP port ( IN_A, IN_B, IN_C : inbit; OUT_Z : outbit ); end component; componenet AOI3_OP port ( IN_A, IN_B, IN_C : inbit; OUT_Z : outbit ); end component; begin XOR : XOR3_OP port map (A, B, Cin, Sum); AOI : AOI3_OP port map (A, B, Cin, Cout); end structral; Component

  9. Hirarchical Structure • Can combine 4 fulladder_xx functions (defined earlier) to form another 4-bit fulladder function componentfulladder_st port (A, B, Cin : in bit; Sum, Cout : out bit); end component; signalsig_c0, sig_c1, sig_c2 : bit; begin FA0 : fulladder_dfport map (A(0), B(0), Cin, Sum(0), sig_c0); FA1 : fulladder_bhport map (A(0), B(0), sig_c0, Sum(0), sig_c1); FA2 : fulladder_stport map (A(0), B(0), sig_c1, Sum(0), sig_c2); FA3 : fulladder_bhport map (A(0), B(0), sig_c2, Sum(0), Cout); endhirarchical; entityfulladder_4bitis port (A, B : in bit_vetcor (3 downto 0); Cin : in bit; Sum : out bit_vetcor (3 downto 0); Cout : out bit); endfulladder_4bit ; architecturehirarchicaloffulladder_4bitis componentfulladder_df port (A, B, Cin : in bit; Sum, Cout : out bit); end component; componentfulladder_bh port (A, B, Cin : in bit; Sum, Cout : out bit); end component;

  10. Example of a four-bit register entityreg4is port ( en, clk : in bit; d : in bit_vector (3 downto 0); q : out bit_vector (3 downto 0)); end reg4; • Let us look at a 4-bit register built out of 4 D latches

  11. Behavioral Description of Register architecturebehaviorofreg4is begin process variablestored_d : bit_vector (3 downto 0); begin if (en = ‘1’ andclk = ‘1’) then stored_d(3) := d(3); stored_d(2) := d(2); stored_d(1) := d(1); stored_d(0) := d(0); endif; q(3) <= stored_d(3); q(2) <= stored_d(2); q(1) <= stored_d(1); q(0) <= stored_d(0); wait ond; end process; endbehavior;

  12. Structral Composition of Register entityd_latchis port (d, clk : in bit; q : out bit); end d_latch; architecturearch_dff ofd_latchis begin process (clk) begin if (clk = ‘1’) then q <= d; end if; end process; end arch_dff; entityand2_op is port ( x, y : in bit; z : out bit); endand2_op; architecturearch_and2ofand2_op is begin z <= xand y; endarch_and2;

  13. Structural Description of Register architecturestructofreg4is componentd_latch port (d, clk : in bit; q : out bit); end component; componentand2_op port (x, y : in bit; z : out bit); end component; signalint_clk : bit; begin DFF3 : d_latchport map(d(3), int_clk, q(3)); DFF2 : d_latchport map(d(2), int_clk, q(2)); DFF1 : d_latchport map(d(1), int_clk, q(1)); DFF0 : d_latchport map(d(0), int_clk, q(0)); AND : and2_opport map(en, clk, int_clk); endstruct;

  14. Mixed Models • Models need not be purely structural or behavioral • Often it is useful to specify a model with some parts composed of interconnected component instances and other parts using processes • Use signals as a way to join component instances and processes • A signal can be associated with a port of a component instance and can be assigned to or read in a process

  15. Example of Mixed Modeling : Multiplier

  16. entitymultiplieris port ( clk, reset : in bit; multiplicand, multiplier : in integer; product : out integer); end multiplier; architecturemixedofmultiplieris signalpartial_product : integer; signalfull_product : integer; signalarith_control, result_en, mult_bit, mult_load : bit; compononentshift_adder port ( addend, augend : in integer; arith_control : in bit; sum : out interger); end component; compononentshift_adder port ( addend, augend : in integer; arith_control : in bit; sum : out interger); end component; compononentshift_adder port ( addend, augend : in integer; arith_control : in bit; sum : out interger); end component; begin arith_unit: shift_adder port map ( addend => multiplicand, augend =>full_product, sum => partial_product, add_control => arith_control); result : reg port map (d => partial_product, q => full_product, en => result_en, reset => reset); multiplier_sr: shift_reg port map (d => multiplier, q => mult_bit, load => mult_load, clk => clk); product <= full_product; process begin -- sequential statements end process; end mixed; Example of Mixed Modeling : Multiplier

  17. Concurrent Signal Assignment entityXOR2_OPis port (A, B : in bit; Z : out bit); endXOR2_OP; architectureAND_ORofXOR2_OPis begin Z <= ((notA) andB) or (Aand (notB)); endAND_OR; • The signal assignment ‘Z <= ((notA) andB) or (Aand (notB));’ Implies that the statement is executed whenever an associated signal changes value

  18. Concurrent Signal Assignment entityXOR2_OPis port (A, B : in bit; Z : out bit); endXOR2_OP; architectureAND_ORofXOR2_OPis signal INT1, INT2 : bit; begin -- different order, same effect INT1 <= Aand (notB); -- Z <= INT1orINT2; INT2 <= (notA) andB; --INT1 <= Aand (notB); Z <= INT1orINT2; --INT2 <= (notA) andB; endAND_OR; • Above, the first two statements will be executed when A or B changes, and third if Z changes • Order of statements in the text does not matter

  19. Concurrent and Sequential Statements • VHDL provide both concurrent and sequential signal assignments • Example • SIG_A <= IN_AandIN_B; • SIG_B <= IN_AnorIN_C; • SIG_C <= notIN_D; • The above sequence of statements can be concurrent or sequential depending on context • If above appears inside an architecture body, it is a concurrent signal assignment • If above appears inside a process statement, they will be executed sequentially

  20. Data Flow Modeling of Combinational Logic • Consider a parity function of 8 inputs entityEVEN_PARITY is port ( BVEC : in bit_vector(7 downto 0); PARITY: out bit); endEVEN_PARITY; architectureDATA_FLOWofEVEN_PARITYis begin PARITY <= BVEC(0)xorBVEC(1)xorBVEC(2)xorBVEC(3)xorBVEC(4) xorBVEC(5)xorBVEC(6)xorBVEC(7); endDATA_FLOW ;

  21. Alternative Logic Implementations of PARITY • TREE CONFIGURATION architectureTREEofEVEN_PARITYis signalINT1, INT2, INT3, INT4, INT5, INT6 : bit; begin INT1 <= BVEC(0)xorBVEC(1) ; INT2 <= BVEC(2)xorBVEC(3) ; INT3 <= BVEC(4)xorBVEC(5) ; INT4 <= BVEC(6)xorBVEC(7) ; INT5 <= INT1xorINT2; INT6 <= INT3xorINT4; PARITY <= INT5xorINT6; endTREE ;

  22. Alternative Logic Implementations of PARITY • CASCADE CONFIGURATION architectureCASCADEofEVEN_PARITYis signalINT1, INT2, INT3, INT4, INT5, INT6 : bit; begin INT1 <= BVEC(0)xorBVEC(1) ; INT2 <= INT1xorBVEC(2) ; INT3 <= INT2xorBVEC(3) ; INT4 <= INT3 xorBVEC(4) ; INT5 <= INT4xorBVEC(5) ; INT6 <= INT5xorBVEC(6); PARITY <= INT6xorBVEC(7); endCASCADE ;

  23. Alternates Architecture Bodies • Three different VHDL descriptions of the even parity generator were shown • They have the same interface but three different implementation • Use the same entity description but different architecture bodies • architectureDATA_FLOWofEVEN_PARITY is... • architectureTREEofEVEN_PARITY is... • architecture CASCADE ofEVEN_PARITY is...

  24. Test Benches • One needs to test the VHDL model through simulation • We often test a VHDL model using an enclosing model called a test bench • A test bench consists of an architecture body containing an instance of the component to be tested • It also consists of processes that generate sequences of values on signals connected to the component instance

  25. Example Test Bench entitytest_benchis endtest_bench; architecturetest_reg4 of test_bench is signalsig_d, sig_q : bit_vector (3 downto 0); signalsig_en, sig_clk : bit; begin tb_reg4 : reg4port map (sig_en, sig_clk, sig_d, sig_q); process begin d <= “1111”; en <= ‘0’; clk <= ‘0’; wait for 20 ns; en <= ‘1’; wait for 20 ns; clk <= ‘1’; wait for 20 ns; d <= “0000”; wait for 20 ns; en <= ‘0’; wait for 20 ns; …. wait; end process; endtest_reg4 ;

  26. Summary • Structural VHDL • Use of hierarchy • Component instantiation statements • Concurrent statements • Test Benches

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