RISC-V processor IP product line

1. RISC-V processor IP product line

2. Products Configurable and extensible 32/64-bit RISC-V cores BM Series BI Series BR Series BI-651 BI-671 BM-310 BI-350 BR-351 RV32IMAC[F] RV32IMC (planned 2019) RV64GC RV64GC • Linux capable application cores • From tiny to high-end cores • Single, Dual-issue and out-of-order designs • Multi-core support • Microcontroller core • Small and efficient • Low latency interrupts • Configurable for use case • Embedded cores • Latency sensitive apps • High throughput • Real-time capabilities • Workload optimized IoT SoC Sensor Fusion Smart Meters Accelerator control Wearables Advanced IoT nodes, gateways Artificial intelligence Industrial automation Storage applications Networking applications Datacenter applications High performance ctrl Baseband control Modem L2/L3 processing Low latency networking SSD controllers Compute/Accelerator

3. Custom SoC platforms Application processor / AI edge processor Motor control / Predictive maintenance Low Power MCU / Sensor Hub BM Series based BR Series based BI Series based Milandr

4. Partner introduction • 130 IC design engineers • Full cycle ASIC design • Analog RF design • Power management • Backend design • Digital design • IP design • Package design • 150+ completed ASICs • Experience with 22nm-180nm • MCUs, Ethernet, Transceivers, ADC/DAC, RF • New SoCs based on RISC-V! Milandr • Assembly and test house • 50 engineers

5. Custom SoC turnkey design service Processor IP Infrastructure IP Customer requirements Customer IP Mass production chip Milandr +own IP Third party IP

6. Low power MCU / Sensor hub platform • TSMC 180nm • TSMC 90nm LP • RISC-V • Integrated Flash for BOM cost reduction • Main and battery power domains • Voltage/Freq control • ADCs with different precision and speed • Temp sensor On-chip Flash BM series coreplex Power management Voltage Controller DMA Internal RC oscillators Milandr 12-bit SAR ADC UART SPI I2C Your Custom IP PWM Timers RTC WDGs 24-bit ∑∆ADC

7. BM-310 Microcontroller core TCM-A PLIC IRQs BM-310 core CLINT TCM-B • Small, Low power microcontroller • RV32IMC • Machine/User privilege levels • 3-stage pipeline • Configurable interrupt controller Crossbar JTAG External Ports Debug AHB or AXI interfaces

8. Motor control / Predictive maintenance platform • TSMC 90nm LP • Motor control • Predictive Maintenance • Industrial automation Isolated security/crypto subsystem BR series coreplex TRNG BM-310 Key RAM Crypto Acc Your Custom IP On-chip Flash 1 MiB UART, SPI, CAN, I2C Motor Control Acc 12-bit 3xADC 32 channels Milandr Ethernet USB 2.0 PHY 12-bit 3xDAC Battery domain High Freq PWM PMU 3xLDO + DC-DC

9. BR-351 Embedded core TCM-A PLIC IRQs BR-351 core CLINT TCM-B I$ D$ • RV32IMC • Machine/User privilege levels • 10-stage pipeline • Dual-issue in-order • TCMs and caches Crossbar JTAG FP-AHB or FP-AXI External Ports Debug I-AHB or I-AXI D-AHB or D-AXI

10. Application processor platform • TSMC 28nm • TSMC 40nm • Pre-integrated platform with RISC-V application cores • All SoC infrastructure included • Targets • AI edge devices • Gateways • Industrial automation Your Custom IP BI series coreplex SGMII/ RGMII Ethernet MAC + DMA DDRC PCIe UART USB SPI Milandr CAN I2C NAND DDR PHY PCIe PHY PWM I2S Camera

11. BI series Linux capable application cores BI-651 BI-671 BI-350 RV32IMAC[F] RV64GC RV64GC 64-bit Mid-range application core for maximum single thread performance 64-bit Linux capable core targeting high performance in power constrained environment 32-bit Tiny Linux capable core targeting IoT applications

12. BI series core complex Linux capable application cores IRQs PLIC • RV64GC • Multi-core fully coherent configuration • Machine/User/Supervisor modes • 32 KiB 8-way I/D caches • L2 cache 1-2 MiB • Debug module • Platform Level Interrupt Controller • Coherency controller for maintaining coherency with peripherals and accelerators BI series core CLINT JTAG D-cache 32KiB I-cache 32KiB Debug L2 cache 1-2 MiB Coherency controller AXI Periph port AXI System port AXI Front port

13. BI-671 mid-range OoO application core 3 4 2 1 Next PC I$ access I$ hit/ miss Branch Decode • Mid-range performance • 2x comparing single-issue, 1.5x dual-issue designs • Maximize power efficiency for given performance BTB/BHT RAS RAS push 7 10 6 8 5 9 ALU0 MUL Issue Q WB ALU1 DIV iter Issue Q Decode Rename RF access Branch Issue Q LSU Issue Q D$ access

14. BI-671 at a glance • 10 stage pipeline • Fetch 8B per cycle • Decode two instruction per cycle • Reorder buffer 48 entries • Load/Store queues 16 entries each • 4R3W integer register file 64 entries • I-TLB, D-TLB 16 entries each • Hardware page walk 4 entries • 4-way BTB 512 entries • 8-way 32KiB L1 I- and D-caches • Out-of-order issue • 2 ALUs, 1 Branch, 1 Load/Store, 1 FP * including all necessary SRAMs

15. BI-671 at a glance • 1.3-1.4x better performance than ARM A9 and BOOMv2 • On the same performance level with MIPS P5600 • 75-80% of ARM A73, ARM A57, ET Maxion performance

16. BI-671 SPEC2006 performance BI-671 data is preliminary and collected on FPGA prototype bzip2, gcc, mcf – missing data for Zynq-7000 since require 2GiB RAM gobmk, hmmer, libquantum, astar – missing data for BOOMv2

17. BI-651 power efficient application core 3 4 2 1 Power efficient dual issue core High performance in power constrained Linux-capable devices Next PC I$ access I$ hit/ miss Branch Decode RAS push BTB/BHT RAS 7 8 9 10 5 6 RF read RF byp WB ALU0 ALU1 Decode Issue MUL DIV iter LD/ST D$ access

18. BI-651 performance * Late ALU option was disabled for apple-to-apple comparison with SweRV core BI-651 Late ALU option under implementation Cycle-accurate simulation shows similar to SweRV Coremark performance

19. SPEC2006 BI-651 BI-651 data is preliminary and collected on FPGA prototype

20. BI-350 small Linux capable core • Architecture: RV32IMAC[F] • Single instruction issue • Machine, Supervisor and User modes • Configurable caches • Smaller size • Shorter cache line • Narrow memory interfaces • L2 optional • Tiny coherency controller configuration • Configurable BTB, BHT, RAS IRQs PLIC BI-350 core CLINT I-cache 4-32KiB D-cache 4-32KiB JTAG Debug L2 cache 128KiB – 1MiB Coherency controller AXI Periph port AXI System port AXI Front port

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