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45 th Design Automation Conference Anaheim , California. Electric Field Integral Equation Combined with Cylindrical Conduction Mode Basis Functions for Electrical Modeling of Three-Dimensional Interconnects. June 11, 2008 Ki Jin Han*, Madhavan Swaminathan, and Ege Engin
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45th Design Automation Conference Anaheim, California Electric Field Integral Equation Combined with Cylindrical Conduction Mode Basis Functions for Electrical Modeling of Three-Dimensional Interconnects June 11, 2008 Ki Jin Han*, Madhavan Swaminathan, and Ege Engin School of Electrical and Computer Engineering, Georgia Institute of Technology {kjhan, madhavan, engin}@ece.gatech.edu
Contents • Introduction • Cylindrical conduction mode basis functions (CMBF’s) • Electric field integral equation (EFIE) formulation with CMBF’s • Simulation examples • Conclusions
Through-silicon via (TSV) interconnections in a Si substrate* Introduction (1) Background • Interconnections in 3-D integration • Role of interconnections is critical for signal transmission. • Design and modeling of interconnections are important. • Challenges in electrical design of SiP • Modeling of the entire coupling among interconnects in an SiP. • High-frequency modeling, including skin and proximity effects. Bonding wires in a 3-D integration. (Photo courtesy of Amkor Technology, Inc.) Wideband modeling of the entire coupling (between a thousand wires) is required for multi-functional and high-density integrations. * R. Chatterjee, R. Tummala, “The 3DASSM Consortium: An Industry/Academia Collaboration,” online article in http://ap.pennnet.com
Introduction (2) Approach in this Paper • State of the art • Existing modeling tools: Have issues in accuracy or speed for modeling of large number of 3-D interconnects. • Electric field integral equation (EFIE) combined with conduction mode basis function (CMBF)* • Advantages • Describes current density distribution with a few CMBF’s. • Provides simplified equivalent circuit model. • Issues for 3-D interconnect modeling • Not geometrically suitable for 3-D cylindrical structures. • Allocating basis functions is difficult to describe various proximity effects. • Approach in this paper: EFIE combined with cylindrical CMBF • Maintains advantages of the original CMBF-based approach. • Geometrically suitable for 3-D interconnections (bonding wires, through hole vias). • Automatically captures skin and proximity effects. * L. Daniel, J. White, and A. Sangiovanni-Vincentelli, “Interconnect Electromagnetic Modeling using Conduction Modes as Global Basis Functions,” Topical Meeting on Electrical Performance of Electronic Packages, EPEP 2000, Scottsdale, Arizona, Oct. 2000.
CMBF (1) Cylindrical CMBF • Derived from solutions of the current density diffusion equation in a conductor. • The fundamental mode (skin-effect mode) basis captures skin effect. • Two orthogonal higher-order mode (proximity-effect mode) bases captures proximity effects in arbitrary orientations.
Construction of partial impedance matrix The global partial impedance matrix equation (N: number of conductors) EFIE (1) Basic Formulation (1) EFIE (2) Approximationof current densitywith CMBF’s j : conductor index, n: order index q: orientation index (3) Applying innerproduct(Galerkin’s method)
Frequency dependentpart Frequency independentpart EFIE (2) Calculation of Partial Impedances • Partial resistances • The resistance matrix is purely diagonal. • Partial self inductances • Coordinates transform for angular coordinates enables an analytic integral, and address singular points. • Partial mutual inductances • Pre-computation of frequency independent integrals improves efficiency of frequency-sweep simulation.
“Loops” fromproximity-effect modes “Branches” from skin-effect modes EFIE (7) Equivalent Circuit • Interconnects are approximated into cylindrical conductor segment model. • Cylindrical CMBF are used as global basis functions. • Partial resistances and inductances of are computed. • Combined equivalent circuit is constructed.
Y 1 Testing ports 12 11 10 Ground 7 6 5 2 1 X Examples (1) 5 by 5 Via Array (1) • Geometry
10 11 12 10 10 11 11 12 12 5 5 6 6 7 7 5 6 7 G 1 1 2 2 G G 1 2 G 10 10 11 11 12 12 10 10 11 11 12 12 10 11 12 5 5 6 6 7 7 5 5 6 6 7 7 5 6 7 1 1 2 2 G G 1 1 2 2 G G 1 2 G Examples (2) 5 by 5 Via Array (2) • Self & mutual loop inductances • - At low frequencies, all inductances are mainly functions of distance between lines. • - At high frequencies, inductances decrease variously according different proximity effects. Group 1 Group 2 Group 3 Group 4
Examples (3) 10 by 10 Via Array (1) • Geometry Y X
Examples (4) 10 by 10 Via Array (2) All conductors are uniformly excited. 107 Hz 108 Hz 109 Hz
Examples (5) 10 by 10 Via Array (3) +1 volt 107 Hz 108 Hz 109 Hz -1 volt
z y Examples (6) 102 Bonding Wires on 3 Stacked Chips (1) • Geometry • Bonding wires • Material: gold • Diameter: 25 um • Pitch: 60 um - Length Class 1: 1.26 mm Class 2: 0.82 mm Class 3: 0.48 mm Class 1 Class 2 Class 3 z Package height ~ 1.4 mm y x Y. Fukui et al., “Triple-Chip Stacked CSP,” Proc. IEEE ECTC, pp. 385-389, 2000.
Examples (7) 102 Bonding Wires on 3 Stacked Chips (2) • Impedances at 10 GHz • A wire in class 2 is grounded. Class 1 Class 2 Elapsed time for 19 frequency points 81,749 secs (22.7 hrs)(CPU: Intel Xeon 2.8 GHz, RAM: 2 GB) Full modeling of 102 bonding wires is not available with existing tools! groundedconductor Class 3
Conclusions (1) Conclusions • EFIE combined with the cylindrical CMBF’s • Captures skin and proximity effects with a small number of basis functions. • Geometrically suits various 3-D interconnects: • Wire bonds, connecter pin array, and through hole via interconnects • Improvements in computation of partial impedances • Using analytic expressions, pre-computation for frequency-independent parts, and efficiency enhancement schemes. • Large 3-D interconnect structures can be modeled with the proposed method. • Future Work • Inclusion of capacitive coupling and finite ground effect. • Extension of the proposed method for modeling of TSV.
Acknowledgements Mixed Signal Design Tools Consortium(MSDT) at the Packaging Research Center,Georgia Institute of Technology Matsushita EPCOS Infineon Sameer NXP