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The new H-RORC

H-RORC. The new H-RORC. H-RORC Prototype. PCI 3.3 V form factor 12 layers, 6 routing layers 2 SIU/DIU connectors. H-RORC. H-RORC : HLT Read-Out Receiver Card Tasks: Receiving of the raw detector data Injecting the data into the main memory of the hosts of the HLT framework

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The new H-RORC

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  1. H-RORC The new H-RORC

  2. H-RORC Prototype • PCI 3.3 V form factor • 12 layers, 6 routing layers • 2 SIU/DIU connectors

  3. H-RORC H-RORC : HLT Read-Out Receiver Card Tasks: Receiving of the raw detector data Injecting the data into the main memory of the hosts of the HLT framework Online processing of the data in hardware Sending processed data out of the HLT Implementation: PCI card 64bit/66MHz with XILINX Virtex4 2 (half) Common Mezzanine Connectors (CMC) 2 fast serial links : TAGNET DDR-SDRAM / ETHERNET / FLASH

  4. H-RORC Details RORC functionality Xilinx Virtex4 LX40 FPGA “SecureConfiguration” with FLASH memory and CPLD PCI interface with 64 bit / 66MHz – XILINX LogiCORE 2 x half CMC interface to two SIU/DIU cards fast serial links to connect multiple RORCs Additional functionality 4 independent DDR-SDRAM modules with up to 1Gb Optinal Xilinx Prom for standalone programming “Ready for Linux” (Ethernet interface, RS232, FLASH memory)

  5. Overview Memory Configuration DDR-SD DDR-SD USER- FLASH XC95144 CPLD CMC-J11/J22 DDR-SD CFG- FLASH DDR-SD CMC-Connector CMC-Connector OSC Serial links XILINX VIRTEX4 LX40 RS-232 PLATFORM PROM ETH-PHY LVDS links Power 1V2 POWER Power 1V8 TAGNET OSC TAGNET Power 2V5 PCI-66/64 PCI-Power 3V3

  6. Overview: RORC Functionality only Memory Configuration DDR-SD DDR-SD USER- FLASH XC95144 CPLD CMC-J11/J22 DDR-SD CFG- FLASH DDR-SD CMC-Connector CMC-Connector OSC Serial links XILINX VIRTEX4 LX40 RS-232 PLATFORM PROM ETH-PHY LVDS links Power 1V2 POWER Power 1V8 TAGNET OSC TAGNET Power 2V5 PCI-66/64 PCI-Power 3V3

  7. FPGA Details 41.472 Logic Cells 288 kb distributed RAM ( 18.432 x 16bit) 1728 kb dual-port block RAM (96 x 18 kBit) 64 DSP slices: 18x18 two’s complement multiplier 48bit accumulator & adder/subtracter 8 Digital Clock Manager (DCM) 4 Phase-Matched Clock Dividers (PMCD) 640 User I/Os Flexible I/O technology : i.e. PCI, DDR, DDR2 partial/full reconfigurable while operating

  8. PCI Test setup H-RORC HOST-PC Virtex4 ChipScope DMA controller HOST MAIN MEMORY PCI Core 64/66 PCI-BUS LINUX-KERNEL Catalyst TA600 PCI Tracer Tracer-SW Internal Mem 4 KByte Terminal A HOST is equipped with a H-RORC and a PCI tracer. The transaction can be monitored by normal output to a terminal, a PCI tracer and inside the FPGA by using the ChipScope logic analyzer

  9. 64bit Master Read • Start of a 64bit PCI read burst from address 0x01587000 initiated by the H-RORC • PCI-bus activity monitored by external tracer • 4 64bit words are transmitted by the target before disconnect wo. data As seen in the 32bit master read, the chipset disconnects a memory read after 32 bytes of transfered data -> Internal buffer of the chipset

  10. DMA Write Performance Measured performance of DMA data cycles on the PCI bus. • Theoretical bandwidth of a 64bit/66MHz PCI bus: • 528 MByte/s For each DMA block length 10/100/1000/10000 transactions have been performed The time for each transaction was measured by a counter with a 15ns granularity The transmitted data was checked for errors: No errors occured

  11. DIU-PCI Test Setup CHIPSCOPE DIU H-RORC DDL SIU HLT-RORC MAIN- MEM MAIN- MEM PCI-TRACER SENDER RECEIVER Terminal PCI-TRACER SW Terminal The sender simulates a data source and sends data via the SIU-DDL-DIU to the H-RORC which stores the data in the main memory via PCI DMA

  12. DIU Test results The DIU was operated with 66MHz. A full synchronization scheme was used to synchronize with the PCI clock Command sequences were send to the DIU via PCI to open a link Data was send by the SIU to the DIU. Verification of the data was done with ChipScope, PCI tracer and by comparing the data automatically. Different test patterns were used: - ramp - walking one - A5A5A5A5

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