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PC Based Spectrum Analyzer. Phase III. May03-10. Client: Teradyne Inc. Faculty Advisor: Dr. DJ Chen. Michael Cain Paul Heil Eric Rasmussen Aung Thuya. April 29, 2003. Acknowledgements. The team would like to thank: Teradyne Steve Miller Dr. Degang Chen. Presentation Outline.
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PC Based Spectrum Analyzer Phase III May03-10 Client: Teradyne Inc. Faculty Advisor: Dr. DJ Chen Michael Cain Paul Heil Eric Rasmussen Aung Thuya April 29, 2003
Acknowledgements • The team would like to thank: • Teradyne • Steve Miller • Dr. Degang Chen
Presentation Outline Problem Statement Operating Environment Intended Use and Users Assumptions and Limitations End Product Accomplishments Approaches Research Design Implementation Testing Resources and Schedules Closing Materials
List of Definitions DAC – digital to analog converter DC offset – DC voltage in an AC signal FPGA – field programmable gate array Spectrum analyzer – measures magnitude of signal harmonics THD – total harmonic distortion
Problem Statement Amplifier for PC Based Spectrum Analyzer • 100MHz high gain, low noise, low distortion • Programmable DC offset and frequency response calibration
Problem Statement (cont’d.) DC — 1kHz Input +/- 5 volts 6, 20, 40, 60 +/- 10 volts 0.05 dB < - 105 dB Total 1.5 nV/rtHz Input Voltage Available Max Output Freq Response Harmonic > 1kHz - 20 kHz +/- 5 volts 6, 20, 40, 60 +/- 10 volts 0.05 dB < - 95 dB 1.5 nV/rtHz Frequency Range Gain Settings Voltage Flatness Distortion Noise > 20kHz - 100kHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < -85 dB 2.5 nV/rtHz Range (Volts) (dB) (Volts) (dB) (dB) (nV/rtHz) > 100kHz - 1MHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < - 80 dB 3.5 nV/rtHz > 1MHz - 10MHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < - 70 dB 3.5 nV/rtHz > 10MHz - 20MHz +/- 2.5 volts 6, 20 +/- 5 volts 0.10 dB < -65 dB 3.5 nV/rtHz > 20MHz - 50MHz +/- 1.0 volts 6, 20 +/- 2.0 volts 0.10 dB < -50 dB 5.0 nV/rtHz > 50MHz - 100MHz +/- 1.0 volts 6, 20 +/- 2.0 volts 0.10 dB < -40 dB 5.0 nV/rtHz
Operating Environment Normal lab conditions Low humidity, room temperature
Intended Users and Uses Users will be Teradyne test engineers Use will be preamplifier for PC Based spectrum analyzer
Assumptions • Users • Teradyne test engineers are familiar with the operation of a spectrum analyzer • Requirements • Specifications are attainable • Financial Budget • Teradyne will cover project costs
Limitations • Hardware • Noise and distortion trade-off • Must have a stable configuration • Software • Simulation software limitations • Technical Knowledge • No experience with PC board fabrication
End Product • The end product will consist of the following deliverables: • Analog amplifier design with embedded digital controls • Software for the embedded digital controls • Design and user documentation
Present Accomplishments • Research – 100% completed • Analog amplifier design – 100% completed • Digital controls – 100% completed • Software controls – 100% completed • Simulations – 100% completed • Fabrication – 0% completed • Testing – 0% completed
Approaches Considered and Used • Amplifier Topology • Low noise amplifier (LNA) • Operational amplifier in resistive feedback
Approaches Considered and Used (cont’d.) • DC Offset Correction • Clocked ping-pong structure • Offset voltage referral • Successive approximation scheme
Approaches Considered and Used (cont’d.) • Frequency Response Calibration • Automatic • Manual
Project Definition Activities • Project scope was changed to a paper design • Occurred after design was submitted for fabrication • Will be completed by future team
Research Activities • Amplifier Topologies • Operational Amplifiers • DACs • FPGAs • Digital Potentiometers • Comparators
Design Activities Amplifier Design
Design Activities (cont’d.) DC offset correction
Design Activities (cont’d.) Frequency response calibration
Implementation Activities Implementation was not necessary
Testing Activities PSpice simulations for analog design Verilog simulations for digital state machine
Other Significant Activities User manual Estimated performance analysis Design vault on CD
Resource Requirements Personal Effort
Resource Requirements (cont’d.) Item Team Hours Other Hours Cost Board Fabrication 0 0 $0 Components 0 0 $0 Project Poster 10 0 $48 Total 10 0 $48 Total Cost
Schedule Project Schedule
Project Evaluation • Schematic level implementation – fully met • Simulations – fully met • Fabrication – not attempted • Testing – not attempted
Commercialization • Only one will be fabricated for testing purposes • Will be a part of Teradyne’s Integra J750 • Cost of J750 starts at $99,000
Recommendations for Future Work • Meet low noise requirement • Make frequency response calibration automatic • Fabricate board • Complete testing
Lessons Learned • Set up weekly meetings with client and team • Do not procrastinate • Make sure design tools are adequate • Do not be too optimistic with scheduling • Do not be too elaborate with complicated designs
Risk and Risk Management • Losing a team member • No available times for meetings • Parts ordered on time • Sending design to fabrication on time
Closing Summary Learned a lot about amplifier topologies Team skills improved Useful information passed to next group