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SPD Very Front End Board

SPD Very Front End Board. Very Front End Board- Test Functionality (I). Very Front End Board- Test Functionality (II). Very Front End Board- Status. Design has been splitted into two different boards: PMT + ASICs + FPGA + Transceivers +DACs

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SPD Very Front End Board

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  1. SPD Very Front End Board

  2. Very Front End Board- Test Functionality (I)

  3. Very Front End Board- Test Functionality (II)

  4. Very Front End Board- Status • Design has been splitted into two different boards: • PMT + ASICs + FPGA + Transceivers +DACs • Level Shifter + Serializer + Cable Compensation + • Output Connectors + Input Connector + Power Supply • Connector • Size of both boards: 12cm x 8cm

  5. Very Front End Board- First Board (I)

  6. Very Front End Board- First Board (II)

  7. Very Front End Board- Second Board

  8. Very Front End Board- Mapping (I) PMT ( Top View in VFE Board): Note: Gnd at Bottom

  9. 17 33 37 53 49 21 5 1 57 25 61 45 13 9 41 29 ASIC1: ASIC2: ASIC7: ASIC6: ASIC4: ASIC3: ASIC8: ASIC5: 22 2 50 38 54 6 18 34 10 1415 46 62 58 30 26 42 23 3 39 7 19 55 51 35 63 47 59 11 43 27 31 4 20 24 56 8 40 36 52 60 44 64 32 12 48 16 28 Very Front End Board- Mapping (II) ASICs Mapping: Note: Odd ASICs are in top layer. Even ASICs are in bottom layer.

  10. Very Front End Board- Mapping (III) Serializers Mapping: S1: S3: S2: S4:

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