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AMC – Adaptive Mirror Controller

Project duration – 1 year. AMC – Adaptive Mirror Controller. Project supervised by: Mony Orbach Project performed by: Koren Erez, Turgeman Tomer. Introduction. The project is a collaboration between the Physic ’ s Adaptive Optics Lab and HS DSL.

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AMC – Adaptive Mirror Controller

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  1. Project duration – 1 year AMC – Adaptive Mirror Controller Project supervised by: Mony Orbach Project performed by: Koren Erez, Turgeman Tomer

  2. Introduction • The project is a collaboration between the Physic’s Adaptive Optics Laband HS DSL. • Developing a system that controls adaptive mirrors, by changing the voltage of their capacitors (up to 128 capacitors).

  3. The Optical System

  4. Signals & Rates Input: • A serial signal from the computer through a USB. Output: • 128 outlines of analog signal (0-295V). Rate: • The system will update all 128 outputs in 1mSec.

  5. USB Optical Device Adaptive Mirror External Flow Chart AMC

  6. AMC MMC USB 8bit 8bit 8bit 8bit 8bit 8bit 8bit 8bit 123Byte 122Byte 123Byte 126Byte 125Byte 120Byte 128Byte 127Byte 124Byte 121Byte 12bit 12bit 12bit 12bit 12bit 12bit 12bit 12bit Amp. Amp. Amp. Amp. Adaptive Mirror Internal Flow Chart Internal Flow Chart – Data flow USB Interface FPGA Meanwhile, all the Bytes moved from the computer to the AMC. D/A

  7. Withstanding user demands Square root conversion of the input data: • 12bit D/A instead of 8bit. • Selection of 256 values from 4096, using a LUT in the FPGA. 1msec for loading 128 capacitors: • D/A with 4 outputs interface. • Four HV Amp – 75% time saving.

  8. Control lines 40 Control/Data lines are required from the MMC: D/A 12 Data + 1 WR +2 Address = 15 HV Amp. x4 (1 EN + 5 Address) x 4 = 24 Power-up/down sequence = 1 Problem: The MMC have only 20 outputs. Solution: • The address and EN lines of all four HV will be common. • Sequential timing of the D/A & HV, and therefore the HV Address lines and 5 of the D/A Data lines will be common. • Total required lines: 15(D/A) +1(HV Amp. EN) + 1(Power-up) = 17

  9. Software FPGA - VHDL programming: • Controller. • LUT. USB Driver: • Supplied by the DLP manufacturer. C++ function: • Bytes transfer from user to the USB stack.

  10. Tests Software tests: • VHDL simulation of the timing, and the control lines value. Hardware tests : • Step-by-step system functionality test. • USB rates.

  11. Milestones • 25.01.06– Power-up circuit design. • 01.02.06 – Cyclone & Transceivers studying. • 07.02.06 – Pin to pin scheme. • 21.02.06 – FSM Design. • 28.02.06 – VHDL initial writing. • 01.03.06 – Wiring and initial checking. • 08.03.06 – Final A report.

  12. System’s Components-MMC The MMC contains: • USB245M. • FPGA - Cyclone by Altera. • Transceivers.

  13. System’s Components-USB • USB245M- USB to FIFO, parallel interface communication module, by DLP Design. Rate: • up to 1MByte/sec. Power: • 5V from USB cable.

  14. System’s Components-USB

  15. System’s Components-FPGA • Cyclone - 144 pin FPGA by Altera. Functionality: • Controls all system’s components. • Converts 8 bits of data to 12 bits, by a look up table. Power: • Vccint = 1.5V , Iccint = 150mA (for initializing only). • Vccio = 3.3V , Iccio = 4mA.

  16. System‘s Components-D/A AD5344 –12-Bit Parallel Interface, Quad Voltage-Output DAC.

  17. System‘s Components-D/A Rate: • Up to 230KHz Power: • Vref = 4.1V, Rref = 180khom.  (for 4 Vref entries) Pref = 0.4mW. • Vdd = 5V, Idd = 600uA.  Pdd = 3mW.

  18. System’s Components-Amp. Four HV257 – 32 channel High Voltage Sample-and-Hold Amplifier array.

  19. System’s Components-Amp. Rate: • Up to 230KHz External power supply: • Vpp = 300V, Ipp = 0.8mA. • Vdd = 6.5V, Idd = 4.3mA. • Vnn = - 6V, Inn = -5.2mA. • Total Power = 0.3W. POWER-UP-seq: Vpp->Vnn->Vdd->inputs&anode POWER-DOWN-seq: inputs&anode->Vdd->Vnn->Vpp

  20. 256 Selected values 12 bit D/A Square root Output 12bit D/A Output 8bit D/A Output

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