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Post-Placement Pin Optimization. J. Westra and P. Groeneveld Eindhoven University of Technology. Outline. Introduction Improving Pin Assignment Depth Experimental Results Future Work Conclusions. Introduction. Pin assignment has significant impact on wire length.
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Post-Placement Pin Optimization J. Westra and P. Groeneveld Eindhoven University of Technology
Outline • Introduction • Improving Pin Assignment • Depth • Experimental Results • Future Work • Conclusions
Introduction • Pin assignment has significant impact on wire length. • It is the process of placement of pins on the boundary of a chip or macro. • The focus is on improving pin positions after placement.
Introduction • Routability depends heavily on total wire length. • The proposed pin optimization techniques can be applied for two objectives: • Reduction of total wire length after replacement. • Finding a feasible solution for the pin constraints set by designer.
Introduction • A typical large hierarchical design contains many macros at the boundary of the chip. • The pins on the macro boundaries serve as the interface between the inside and the outside of the macro.
Introduction • Bottom-up pin assignment leads to unnecessary long wires at the top-level. Looking from inside a macro, pins may be placed optimally. From a global view, other pin positions may be better.
Introduction • Bad pin assignment can cause congestion (vertical). • Also in the presence of other congestion. • Good pin planning can solve congestion problems.
Improving Pin Assignment • Pin optimization as an assignment problem • Many pins are competing for a limited number of attractive positions. • Note that such pin optimization only affects the length of pin-nets and the optimization potential is very limited.
Improving Pin Assignment • Wire length estimates of a pin-net after placement are usually based on the size of the bounding box of the net. • Before pin assignment, a pin i does not have a position, and the cost of a position o is: • bbox(pin_net(i)/i) is the bounding box of the pin-net without the pin. • Minimization of the costs is equivalent to minimization of half-perimeter wire length.
Improving Pin Assignment • Depending on the distance to the bounding box of the cells, potential pin positions get costs associated with them. • The two leftmost positions are at a vertical distance of 1, the rightmost has an additional horizontal distance of 4.
Improving Pin Assignment • The pin assignment problem is modeled as a graph. • Nodes represent the pins and positions. • Between each pin-node i and position-node o, an edge with weight c(i, o) exists. • The objective is to select a set of edges S such that the sum of edge weights is minimal. • Each pin-node is adjacent to exactly one selected edge, and each position-node is adjacent to maximally one selected edge.
Improving Pin Assignment • Where I and O are sets of pin-nodes and position-nodes respectively. |O|≥|I| • The problem as defined above is a linear assignment problem.
Improving Pin Assignment • Incorporating top-down pin constraints • Edges are removed if a pin can not be assigned to a certain positions
Improving Pin Assignment • Sometimes, problems can be solved by combining the pin assignment of two macros. • Two assignment graphs can be combined by introducing a “dummy” pin-node for pin-pairs that need to be aligned. • E.g., pins p1 and p2 are treated as a single pin.
Depth • The pin optimization procedure as described in the previous section adjusts pin positions to a given cell placement. • Small adjustments to pin positions have larger impact on positions of cell near to the pins than on cells further away. • Adjusting the pin position to the closest cell does not necessarily yield the best wire length.
Depth • The topological distance between a cell c and a pin i is the minimum number of nets that is used to reach the cell from the pin. • The depth of a cell c is defined as the minimum of the topological distance to any pin: where P is the set of all pins in the circuit.
Depth • At first glance, the pin position is ideally adapted to the cell placement. • However, if the pin is adapted to the position of cells deeper in the circuit, after partial replacement, better overall wire length results.
Depth • Adjusting pins to cells at a specific depth. • Potentially, this could lead to higher wire length right after pin optimization. • Only after restructuring of the placement a reduction would be found.
Depth • In order to experimentally verify to which depth pin positions are best adapted, a depth-first search algorithm is employed in this work with varying depth.
Experimental Results • Experimental setup • The proposed placement flow with pin optimization is compared with a traditional placement flow.
Experimental Results ISPD02 placement benchmarks.
Experimental Results The results of the first comparison in wire length.
Experimental Results The results of the second comparison in wire length.
Experimental Results PPPO represent the wire length after pin optimizations a and b. Pin optimization improves wire length by 0.55% and 0.2%. This clearly shows that the improvements are due to restructuring of the placement rather than direct gains due to adaptation of pin positions to placement.
Future Work • The fact that no specific depth outperforms the other depths: • It is possible to determine depth dynamically, based on local circuit topology. • The position of p1 should be based on the position of the gate at depth 1. • While the position of p2 should be based on the position of the gate at depth 3.
Conclusions • A method for post-placement pin optimization is presented. • The reduction is not merely due to adjustment of pins to the placement, but mainly due to the restructuring of cell placement.
