A New Successive Approximation Architecture for Low-Power Low-Cost A

1. 1 A New Successive Approximation Architecture for Low-Power Low-Cost A/D Converter IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.38, NO.1, JANUARY 2003 Chi-sheng Lin and Bin-Da Liu, Senior Member, IEEE ????:??? ? ?:???

2. 2 Outline Abstract Introduction Basic architecture of successive approximation ADC The ISA (improved successive approximation) -ADC circuit design System design of the parallel - like ISA - ADC Low � voltage circuit design of the ISA � ADC Experimental result Conclusion

3. 3 Abstract A new 6-bit 250MS/s analog-to-digital converter is proposed for low-power low-cost CMOS integrated system. The experimental results indicate that this ADC works up to 250MS/s with power consumption less then 30mW at 3.3V. The ADC occupies only 0.1mm2 with the TSMC 0.35-�m single poly quadruple metal (SPQM) CMOS technology.

4. 4 Introduction In this paper, a novel circuit for low-power low-cost 6-bit CMOS ADC is presented. Based on the ISA-ADC architecture, a parallel-like ISA-ADC architecture for high-speed low-resolution applications is developed. The proposed converter has a simple hardware design and low-accuracy comparator and therefore, is suitable for low-power low cost standard CMOS technology VLSI implementation.

5. 5 Basic architectures of successive approximation ADC The architecture of a general SA-ADC usually consists of a rail-to-rail analog comparator, a digital-to-analog converter and a successive approximation register (SAR) as show in Fig. 1.