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Selling Xilinx Software vs. Altera

Selling Xilinx Software vs. Altera. Xilinx Academy February 24th, 1999. Volume Requirements By Business. $2/unit 500K units = $1M. $10/unit 100K units = $1M. $100+/unit 10K units = $1M. Price. High Density FPGA. High Volume FPGA. CPLD. Density. XILINX ALTERA

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Selling Xilinx Software vs. Altera

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  1. Selling Xilinx Software vs. Altera Xilinx Academy February 24th, 1999

  2. Volume Requirements By Business $2/unit 500K units = $1M $10/unit 100K units = $1M $100+/unit 10K units = $1M Price High Density FPGA High Volume FPGA CPLD Density

  3. XILINXALTERA vs. FLEX 6K vs. FLEX 10K vs. Raphael vs. MAX PLUS+

  4. Xilinx SoftwareHow to Compete and Win Against Altera Advantage!

  5. Xilinx Software Advantage! • Intuitive Design Environment; Easy to Use • Superior HDL Design Solutions • Best Push-Button Results plus Performance Driven “When You Need it” • Best Value Software Configurations

  6. Xilinx Software Advantage! • Intuitive Design Environment; Easy to Use Superior HDL Design Solutions • Superior HDL Design Solutions • Best Push-Button Results plus Performance Driven “When You Need it” • Best Value Software Configurations

  7. Xilinx Ease-of-Use Advantage! XilinxAltera Push Button Design Flows Design Wizards Graphical State Diagram Entry High Volume Solution Interactive Web Enabled Software 4 4 4Very Limited 4 NO! 4 Limited Device Support Proprietary Synthesis 4 NO!

  8. Xilinx Software Advantage! • World-Class EDA Technology, Intuitive Design Environment • Superior HDL Design Solutions • Best Push-Button Results plus Performance Driven “When You Need it” • Best Value Software Configurations

  9. Express Feature Synopsys Synthesis VHDL and Verilog Included Robust Language Support Synthesis Constraint Entry & Timing Analysis HDL Centric Project Management Advantage! Xilinx Altera 4 NO! 4 Choose 1 4 NO! 4 NO! 4 NO!

  10. Xilinx Software Advantage! • World-Class EDA Technology, Intuitive Design Environment • Superior HDL Design Solutions • Best Push-Button Results plus Performance Driven “When You Need It” • Best Value Software Configurations

  11. Push-Button Design Advantage! Runtime in Minutes Performance in MHz Default 42% 4% 3% 9% 44% • 20 HDL designs ranging from 5K to 100K gates • XC4000XL-08 vs. 10KA-1, Alliance Series 1.5 vs. Max+PLUS II v9.01 • Runtimes are place and route only on 400MHz Pentium II

  12. Performance Driven Design Advantage! Xilinx Altera 4 Robust Constraints Language NO! 4 Robust Timing Reports NO! 4 4 Floorplanner 4 Min Timing NO! 4 Temp / Voltage Prorating NO! 4 Revision Control NO!

  13. Xilinx Software Advantage! • World-Class EDA Technology, Intuitive Design Environment • Superior HDL Design Solutions • Best Push-Button Results plus Performance Driven “When You Need It” • Best Value Software Configurations

  14. Volume Requirements By Business $2/unit 500K units = $1M $10/unit 100K units = $1M $100+/unit 10K units = $1M Price High Density FPGA High Volume FPGA CPLD Density

  15. $4,995! $95, $495 Target Markets / Solutions ALI-STD $495! FND-EXP FND-BSX FND-BAS FND-BSX Price High-End FPGA High-Volume FPGA CPLD Density

  16. Entry Level Software Unequaled Value 4 FND-BAS / PLS-ES / PLS-WEB NEW WebFitter XABEL Synthesis (BAS) VHDL/Verilog Synth (WebFitter) Functional & Timing Simulation CPLDs & High Volume FPGAs included! $95 Free download from Web Proprietary AHDL Synthesis No VHDL / Verilog Synthesis No Simulation No FPGAs, No 6K or 9K Support Free Site-License after PLS-BASE purchase ($995) 4 4 4 4 4 4 4 F1.5 vs. Max+plus II 9.0

  17. High Volume Software Unequaled Value 4 FND-BSX PLS-BASE Synopsys Synthesis VHDL and Verilog HDL Support Best Push-Button Results (Non-TD, Same Constraint TD) A.K.A. Speed Technology Complete CPLD and High Volume FPGA Support Functional & Timing Simulation $495 Proprietary Synthesis Choose One Best Push-Button Results (Non-TD, Same Constraint TD) Basic Timing Driven Tech. 6K, 9K, Timing Driven Optional Functional Simulation Only $995 + $995 ea. PLSM-6K/8K & PLSM-9K Migration Options 4 4 4 4 4 4 4 4 F1.5 vs. Max+plus II 9.0

  18. High End FPGA Software Unequaled Value 4 4 FND-EXP PLS-MAGNUM ALI-STD Synopsys Synthesis VHDL and Verilog HDL Support Best Timing Driven Results A.K.A. Speed Technology HDL Centric Project Mgmt Revision Control Joint Development for Next Generation Flows $3995 ALI-STD / $4995 FND-EXP Proprietary Synthesis Choose One Inferior TD Results Basic Timing Driven Tech. Basic Project Management Basic Project Management Focus on Proprietary Synth $4,995 4 4 44 44 4 4 4 4 F1.5 vs. Max+plus II 9.0

  19. Mainstream designer Productivity is dependent on: Ease-of-Use Run Time High density and high speed designer Productivity is dependent on: User Control Design Performance Design Iteration Time - Run Time Where Is The Value In Software?Customers see value in software that will enable them to get their job done in the fastest possible time. • Productivity through: • Ease-of-Use • Performance Driven Design • User Control.

  20. Where’s the Value in 1.5? Ease of Use • Constraints Editor • Simple control over powerful constraints • Automatic Pin Locking • When you’re ready for board layout • Improved Reporting • Important information first

  21. Graphical Constraints Editor Guides user to the best constraint methodology

  22. Where’s the Value in 1.5? Performance • Minimum Delays • Temperature and Voltage Prorating • Faster performance at more optimal operating conditions • Dramatic Improvements to PAR

  23. Where’s the Value in 1.5? Performance - PAR Improvements • Average 2-3x runtime improvement, 10x on some designs • Faster timing analysis with K-path algorithm • Achieves higher clock rates more easily All this means…. More Turns Per Day Faster Design Cycles

  24. Where’s the Value in 1.5? User Control • Floorplanner • New Constraints • Push Button Performance • Simple control over tradeoff between runtime and performance

  25. Foundation & Alliance SeriesUnparalleled ProductivityKey Features in Version 1.5 • 4 New FPGA/CPLD Families • 50% Runtime Reduction • Graphical Constraints Editor • Floorplanner • Automatic Pin Locking • 6x Faster Timing Analysis (Kpaths algorithm) • New Reporting of Minimum Delays • Voltage and Temperature Speed Pro-rating

  26. Key Messages For Alliance • Standards Based Design Interfaces Allows customers to work in their chosen EDA environment. • A.K.A.speedtmTECHNOLOGY Faster compile times and increased clock speed lets customers meet their specifications and get their product to market more quickly. • Integrated Core Generator Software And LogiBLOX Customers can achieve higher performance and get their designs done faster. • World Class Technical Support Instant support over the Web and via the phone to assist customers in completing designs.

  27. Key Messages For Foundation • Complete Front-To-Back Design Environment The tightly integrated tool set makes it easy for customer to learn and use the tools. • Powerful VHDL And Verilog Synthesis - Synopsys FPGA Express Robust language support and optimization technology allows customers to get the most speed out of their design. • Graphical HDL Editor And Integrated Language Wizard Simple graphical tools help to reduce the time it takes for customers to complete their design. • World Class Technical Support Instant support over the Web and via the phone to assist customers in completing designs.

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