DCPS for NSTX-U

1. NSTX-U Supported by DCPS for NSTX-U Coll of Wm & Mary Columbia U CompX General Atomics FIU INL Johns Hopkins U LANL LLNL Lodestar MIT Lehigh U Nova Photonics Old Dominion ORNL PPPL Princeton U Purdue U SNL Think Tank, Inc. UC Davis UC Irvine UCLA UCSD U Colorado U Illinois U Maryland U Rochester U Tennessee U Tulsa U Washington U Wisconsin X Science LLC Culham Sci Ctr York U Chubu U Fukui U Hiroshima U Hyogo U Kyoto U Kyushu U Kyushu Tokai U NIFS Niigata U U Tokyo JAEA Inst for Nucl Res, Kiev Ioffe Inst TRINITI Chonbuk Natl U NFRI KAIST POSTECH Seoul Natl U ASIPP CIEMAT FOM Inst DIFFER ENEA, Frascati CEA, Cadarache IPP, Jülich IPP, Garching ASCR, Czech Rep R.E. Hatcher, K. Ericksonand the DCPS Design Team Princeton Plasma Physics Laboratory NSTX Upgrade Project Office of Science Review LSB B318 October 2nd& 3rd, 2013

2. Background and System Description • The Digital Coil Protection System (DCPS) allows the NSTX-U device to be operated over a wide and complicated operating space. The DCPS is needed to ensure the integrity of the device mechanical structures during operations. • NSTX protection systems used simple (individual coil) mechanisms for protecting coils • NSTX-U requires more comprehensive (sophisticated) methods of protection • Higher performance machine • Longer pulse length • Double the plasma current • Double the toroidal field • New TF, OH, and Divertor coils • Expansion of and reinforcement to the existing mechanical support structures alone was considered but abandoned • Expensive • Complicated • Space considerations • Flexibility

3. Background and System Description (cont.) • Programmable digital system (DCPS) ideal suited to this application • Relatively inexpensive • Ability to protect both coils and structures • Combination coil and structure limits → complex shaped operating region • Extensibility and maintainability is key • DCPS repeatedly executes a set of protection algorithms utilizing a modern digital computer system to constrain operations within a complex operating envelope • NSTX-U will use a combination of mechanical reinforcement, periodic field inspection, and the DCPS to ensure the mechanical integrity of the NSTX-U device mechanical structures

4. System Block Diagram Water Systems PLC Pulse Duration and Period Timer

5. Deliverables • New (upgraded) Pulse Duration and Period (PDP) time unit • New (upgraded) Water Systems PLC • DCPS computer system and hardware interface including data acquisition components • DCPS software system with Graphical User Interface (GUI) and support for standalone simulation / scenario development • DCPS Auto-Tester unit that supports end-to-end system testing • DCPS Auto-Tester software system including GUI • Verified base set of protection algorithms • Standalone codes for algorithm verification / scenario development • System documentation (manuals, operating procedures, etc.)

6. Project Team / Staffing R. Hatcher – Project leader, EE Design P. Titus – Analysis support, Engineering Analysis Branch (Branch Head) K. Erickson – Software Design Lead Engineer, IT Dept. R. Mozulay – PDP Timer Design Lead Engineer, EE Design X. Zhao – Water Systems PLC Lead Engineer, EE Design H. Schneider – Hardware System Interface, EE Design J. Dong – Auto-Tester Hardware Lead Engineer, IT Dept. G. Tchilingurian, S. Lynch. W. Davis - Software Engineer, IT Dept. G. Zimmer – Auto-Tester Software Lead Engineer, IT Dept. S. Gerhardt – Physics support W. Que – DSP programming support, EE Design P. Sichta – Computer Hardware support, IT Dept. (Branch Head)

7. Subsystem Status Water Systems PLC Pulse Duration and Period Timer

8. Subsystem Status (cont.) • PDP Timer • New system adds upgraded period and duration timing flexibility and accuracy • New design fully vetted (successful CDR, PDR, and FDR) • Two PC boards (1 + spare) fabricated, stuffed, and bench tested • One unit fully assembled in chassis awaiting installation • Water System PLC • New system supports monitoring of all coil outlet temperatures • New design fully vetted (successful CDR, PDR, and FDR) • Procedure for existing equipment removal / modification written and reviewed • Work in Test Cell and Test Cell basement started • System fabrication started (parts ordered, minor assembly started) ~ 30 % complete • Auto-Tester Hardware • Detailed interconnection diagram developed • Auto-Tester computer and I/O cards procured and delivered to software engineer • Channel assignment defined (spreadsheets) for DCPS computer and Auto-Tester • FDR pending

9. Subsystem Status (cont.) • Auto-Tester Software • Labview chosen for Auto-Tester software development platform (multiple users, proven expertise) • Labview VI front panels (the GUI) have been laid out, and are navigational. • The two types of I/O cards have been tested and shown to support all required modes of operation • National Instruments Analog Output device • National Instruments Digital Input / Output device • A waveform editor is being written in Matlab and a method of sending / receiving profiles to / from has been developed (same waveform editor will be used by main DCPS software) • Overall ~40 % complete (FDR pending)

10. Subsystem Status (cont.) Water Systems PLC Pulse Duration and Period Timer

11. Subsystem Status (cont.) • Hardware Interface • Creates interface to the DCPS computer from both the Auto-Tester and the device coil current signals, clocking signals, and some supplemental I/O • Creates interface from the DCPS computer to the HCS system (L1 fault) • Provides mechanism for resetting DCPS system after a fault (key + pushbutton) • Overall ~40 % done (FDR pending) • Analysis and Algorithm Development • Machine design based on 96 static scenarios (Menard) • Algorithms developed to protect coils and other mechanical structures • Basic set of algorithms checked against 96 scenarios (spreadsheet) • Algorithm parameter data sheets developed and submitted to Engineering and IT dept. (Gerhardt / Titus) • Standalone (interpreted language) simulation codes developed for algorithm verification and scenario development / simulation (Gerhardt / Hatcher) • Real-time algorithm implementation ongoing (initial tests successful, cycle time < 100 µs)

12. Interconnection Components COIL CURRENTS, Ip & SPARE 32 TOTAL DCPS REAL TIME PC HARDWARE USER INTERFACE DCCT’s COMMAND DCCT’s PROTECTION HALMAR SIGNAL CONDITIONER TO/FROM FCPC TIES THE WHOLE SYSTEM TOGETHER INTERCONNECTION CHASSIS ANALOG AUTO TESTER PC PDP 48 INPUT BUFFER +/-10v, +/-5v 2kHz Anti-Alias Filter KEY CARD (SWITCH) x 5 CROSS- CONNECT CROSS- CONNECT INTERCONNECTION CHASSIS DIGITAL 32 LEMO to 1 MULTI-PIN SCSI LEMO INTERFACE PANEL LEMO INTERFACE PANEL DTACQ TRANSIENT DIGITIZER RTU #1 RTU #2 WATER PLC HARDWARE & SOFTWARE L1 RESET & OVERRIDE TO/FROM FCPC HSC PWR OK DAQ INTERFACE CARD x 13 RECONFIGURABLE TIMING UNIT PROGRAMABLE EVENT GENERATOR HOUSE CLOCK CAMAC REPLACEMENT DIGITAL STATUS ONLY Hans Schneider

13. Algorithms • “Casting” of all algorithms into generic types simplifies implementation – reduces errors and provides consistent user interface • Presently 5 algorithm types are defined – four implemented and checked on prototype real-time system • Cross verification of three scenarios (TRANSP startup scenarios) is ongoing – so far so good! • Basic Algorithms • Post-disruption current prediction • Force calculation • Combined force calculation • Coil moments

14. Algorithms (cont.) • Basic Algorithms (cont.) • TF coil out-of-plane torque • PF coil stresses • Local coil stress (OH) • Coil bolt stresses • Action (I2t) • Algorithm output comparing real-time system and simulation code output (1.6 MA scenarios)

15. Action (I2t) Algorithm Plots

16. Vertical Force (Fz) Algorithm Plots

17. Combined Vertical Force (Comb. Fz) Algorithm Plots

18. Subsystem Status (cont.) Water Systems PLC Pulse Duration and Period Timer

19. DCPS Core and Software • DCPS Core • Prototype computer system with I/O cards installed in FCC (available for testing and development) • RedHawk OS from Concurrent Systems chosen as real-time operating system (includes NightStar tool suite for system tuning and debugging) • DCPS software system was designed in a modular fashion – each component is designed, developed, and verified independently

20. DCPS Software Each component designed and developed independently

21. Component Completion to Date • Minor components have some progress • System Control – 15% • Basic control skeleton stubbed out • All state transitions in place • Security – 40% • User account management facilities designed, policies in place • Secure coding practices identified and employed • Physical security (firewalls, network separation, etc.) implemented • Monitoring – 10% • Real-time logging facility prototyped • Log file analyzer (splunk) implemented

22. Component Completion to Date (cont.) • Major components have significant progress • Algorithms – 80% • All algorithm types implemented • Thread synchronization designed and implemented • Data – 30% • Basic input and output using files completed • Complete shot simulation sequencing with fault recording complete • User Interface – 50% • UI implemented with Qt framework – open-source, large user base, community support, future is bright • Windows exist for all major functions • Post shot analysis external tools called up from the GUI

23. Algorithm Timing Exceeds Requirements • Cycle time goal is 200 µs • Currently, DCPS calculates 550 limit values of various types in less than 75 µs across 17 CPUs • With 25 µs headroom, acquisition can take up to 100 µs • In-house designed C++ thread synchronization idiom coordinates all threads with ~1 µs of overhead per CPU • Minimal optimizations applied so far, opportunities for speed improvements • Room for algorithm expansion without optimization efforts

24. New Thread Synchronization Idiom • Bi-directional Atomic Semaphore Synchronization (BASS) • Waste CPU resources to guarantee instant startup • Use atomic counters to track thread “complete” and “ready” status • Assign manager thread to its own dedicated CPU • Manager signals workers to start (ready) • Waits for “complete” signals • Assign each worker thread to its own dedicated CPU • Spin the CPU waiting for “ready” signal • Send “complete” signal when the work queue is empty

25. Bi-directional Atomic Semaphore Synchronization Worker Thread Manager Thread Worker Thread Wait for start Ready = Workers + 1 Complete = Workers + 1 Notify Start Wait for start Spin Ready > 1 --Ready --Ready Spin Ready > 0 Spin Ready > 0 Complete = Workers + 1; Ready = 0 Spin Complete > 1 Do work Do work --Complete --Complete Spin Complete > 0 Spin Complete > 0 Ready = Workers + 1; Complete = 0

26. Remaining Work • DCPS Pre-operational system testing – February 2014 (to last approximately ~1 month) • “Simple” Auto-Tester operations – local clock, DCPS only (March 2014, approx. 1 week) • Support for FCPC PTP activities (March 2014 – ) • “Real” system parameter settings, MDSPlus tree population, more algorithm tuning, test shot development – 1st quarter CY14 • Collaborate with Physics to establish 1st year operating space parameters (global limit scale factors) • Establish “conduct-of-operations” (how do we operate, change, and maintain the system – operating procedures) – 2nd QTR CY14 • Full Auto-Tester operation (using system clock) – May 2014 • Full system commissioning – June 2014 • More (exhaustive) system testing… – June - August 2014 • Support for NSTX-U PTP & ISTP – September 2014