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Perkenalan Sequensial

Perkenalan Sequensial. Gambaran:. Model Rangkaian Sequensial. x 1. Logika Kombinasional. z 1. z m. x n. Y 1. Y r. y 1. y r. Memori. Memori. 0. 1. 1. 1. Q. B. 1. 0. 1. 0. A=0. Latch. Q. 0. 1. 0. R=0. S=1. Q. 1. 0. 0. 1. R=1. S=0. SR Latch. (Set). Symbol:.

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Perkenalan Sequensial

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  1. Perkenalan Sequensial

  2. Gambaran:

  3. Model Rangkaian Sequensial x1 LogikaKombinasional z1 zm xn Y1 Yr y1 yr Memori

  4. Memori 0 1 1 1 Q B 1 0 1 0 A=0

  5. Latch Q 0 1 0 R=0 S=1 Q 1 0 0 1 R=1 S=0

  6. SR Latch (Set) Symbol: (Reset)

  7. Tabel Kebenaran SR-Latch S(t) R(t) Q(t) Q’ = Q( t+ ) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 x 1 1 1 x Hold Reset Set Forbidden

  8. Timing Diagram S R Q S R Q

  9. R Q S Q SR Latch dengan Gerbang(Gated SR Latch) R Symbol: Clock or enb S CLK

  10. Timing Diagram CK S R Q CK S R Q

  11. Delay Latch X S D Q Symbol: D Q C CLK Q’ R Y

  12. Tabel Kebenaran D-Latch X Y C Q(t) Q’= Q( t+ ) 0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0’ Store D(t) C Q(t) Q+ = Q( t+ ) 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1 x 0 Q(t) Q+ = Q( t+ )

  13. Timing Diagram CK D Q CK D Q

  14. J Q K Q JK Latch J Symbol: Clock K CLK

  15. Tabel Kebenaran JK-Latch J K C Q(t) Q( t+ ) • 0 0 1 Q0 Q0 • 0 1 1 0 0 • 0 1 1 1 0 • 1 0 1 0 1 • 0 1 1 1 • 1 1 1 0 1 Togle • 1 1 1 1 0 Togle • X X 0 Q0 Q0

  16. Timing Diagram

  17. Master-slave SR flip-flop

  18. Prinsip Kerja

  19. Prinsip Kerja

  20. Master-slave D flip-flop

  21. Prinsip Kerja

  22. Master-slave JK flip-flop Q 1 R R-S Latch J R 1 R-S Latch 1 1 P 0 Qm 0 Qs K 0 S Q S 0 Clock

  23. Edge triggered D flip-flop

  24. Edge triggered JK flip-flop

  25. Edge triggered T flip-flop

  26. R R Q Q S S Flip-Flop dan Latch Clock: R Q S CLK

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