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VLSI Arithmetic Adders & Multipliers. Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel. Digital Computer Arithmetic belongs to Computer Architecture, however, it is also an aspect of logic design.
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VLSI ArithmeticAdders & Multipliers Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel
Digital Computer Arithmetic belongs to Computer Architecture, however, it is also an aspect of logic design. The objective of Computer Arithmetic is to develop appropriate algorithms that are utilizing available hardware in the most efficient way. Ultimately, speed, power and chip area are the most often used measures, making a strong link between the algorithms and technology of implementation. Introduction Computer Arithmetic
Addition Multiplication Multiply-Add Division Evaluation of Functions Multi-Media Basic Operations Computer Arithmetic
Addition of Binary Numbers Full Adder. The full adder is the fundamental building block of most arithmetic circuits: The sum and carry outputs are described as: ai bi Full Adder Cout Cin si Computer Arithmetic
Inputs Outputs ci ai bi si ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Addition of Binary Numbers Propagate Generate Propagate Generate Computer Arithmetic
Full-Adder Implementation Full Adder operations is defined by equations: Carry-Propagate: and Carry-Generate gi One-bit adder could be implemented as shown Computer Arithmetic
High-Speed Addition One-bit adder could be implemented more efficiently because MUX is faster Computer Arithmetic
The Ripple-Carry Adder Computer Arithmetic
The Ripple-Carry Adder From Rabaey Computer Arithmetic
Inversion Property From Rabaey Computer Arithmetic
Minimize Critical Path by Reducing Inverting Stages From Rabaey Computer Arithmetic
Ripple Carry Adder Carry-Chain of an RCA implemented using multiplexer from the standard cell library: Critical Path Oklobdzija, ISCAS’88 Computer Arithmetic
Manchester Carry-Chain Realization of the Carry Path • Simple and very popular scheme for implementation of carry signal path Computer Arithmetic
Original Design T. Kilburn, D. B. G. Edwards, D. Aspinall, "Parallel Addition in Digital Computers: A New Fast "Carry" Circuit", Proceedings of IEE, Vol. 106, pt. B, p. 464, September 1959. Computer Arithmetic
Manchester Carry Chain (CMOS) • Implement P with pass-transistors • Implement G with pull-up, kill (delete) with pull-down • Use dynamic logic to reduce the complexity and speed up Kilburn, et al, IEE Proc, 1959. Computer Arithmetic
Pass-Transistor Realization in DPL Computer Arithmetic
Carry-Skip Adder MacSorley, Proc IRE 1/61 Lehman, Burla, IRE Trans on Comp, 12/61 Computer Arithmetic
Carry-Skip Adder Bypass From Rabaey Computer Arithmetic
Carry-Skip Adder:N-bits, k-bits/group, r=N/k groups Computer Arithmetic
Carry-Skip Adder k Computer Arithmetic
Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985) 6 5 5 4 4 3 3 D=9 1 1 Any-point-to-any-point delay = 9 D as compared to 12 D for CSKA Computer Arithmetic
Carry-chain block size determination for a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Delay Calculation for Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Delay model: Computer Arithmetic
Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Variable Group Length Oklobdzija, Barnes, Arith’85 Computer Arithmetic
Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Variable Block Lengths • No closed form solution for delay • It is a dynamic programming problem Computer Arithmetic
Delay Comparison: Variable Block Adder(Oklobdzija, Barnes: IBM 1985) Computer Arithmetic
Delay Comparison: Variable Block Adder VBA CLA VBA- Multi-Level Computer Arithmetic