Power Analysis and Estimation for Digital CMOS Circuits

1. Power Analysis and Estimation for Digital CMOS Circuits Jins Davis Alexander Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, AL 36849 USA VLSI D&T Seminar

2. Motivation For This Work. • An accurate and efficient power estimation tool for CMOS circuits. • To estimate and separate the different components of power dissipation in a single packaged tool. • Knowledge of components of power is useful in design decisions and optimization. • Most existing tools estimate the total power or are specific to a particular power component. VLSI D&T Seminar

3. Outline • Existing Power analysis Tools. • Various power components. • Dynamic Power Estimation. • Leakage (static) power estimation. • Short circuit power estimation. • Experimental Results. • Future Work. • Conclusion. VLSI D&T Seminar

4. Some Power Analysis Tools and Techniques. • PowerMill – transistor level simulator for simulation of current and power from Synopsys. • WattWatcher – RTL level power estimator from Sente. • PowerPlay – dynamic power estimator based on logic simulation. • Crest – pattern independent current estimator. • McPower- monte carlo approach to power estimation. • Spice Simulators – Mentor Graphics tools like Mach PA, ELDO simulator, Silvaco SmartSpice, etc. VLSI D&T Seminar

5. Components of Power Dissipation. • Dynamic • Power due to Signal transitions. • Logic power (due to logic transitions). • Glitch power (due to glitches). • Short Circuit component. • Static • Leakage power (due to leakage currents). • Clock Power VLSI D&T Seminar

6. Power components. Dynamic power Leakage power VDD Ron Short circuit power vi (t) vo(t) CL R=large Ground VLSI D&T Seminar

7. Dynamic Power • Depends on the switching activity of the gate and the load capacitance at the output node (switching capacitance). • Supply Voltage and clock frequency. • Dynamic power = Σ 0.5 αifclk CLiVDD2 All gates i where fclk clock frequency αiactivity factor of gate i CLi load capacitance of gate i VLSI D&T Seminar

8. Dynamic power estimation. • Calculation of logic transitions (events) by means of logic simulation. • Event driven simulation algorithm used. • Calculate energy dissipated for each event for every gate. • Average dynamic power = Total energy/Analysis period. VLSI D&T Seminar

9. Event driven Circular Time Stack max t=0 Event link-list 1 2 3 4 5 6 7 VLSI D&T Seminar

10. Leakage power • Majority of leakage dissipation is due to sub threshold leakage current. VDD IG Ground R n+ n+ Isub IPT ID IGIDL VLSI D&T Seminar

11. Sub threshold current. • Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH)/nVt} (1 - exp(-VDS/Vt) where μ0 effective carrier mobility Cox gate oxide capacitance per unit area L: channel length W: gate width Vt = kT/q: thermal voltage n: a technology parameter VLSI D&T Seminar

12. Leakage power estimation. • Leakage power is input vector dependent. • Analyze which transistors of the gate are in ON state or OFF state during steady state analysis. • Used BSIM3V3 spice models for calculation of threshold voltage, sub threshold currents for nMOS and pMOS transistors. • Weighted time estimation of how long each transistor is in OFF state during the entire simulation period. VLSI D&T Seminar

13. Example of NAND Gate. VDD On Off On Off On Off 0 1 0 On Off Off 1 1 0 On On Off VLSI D&T Seminar

14. Short Circuit Power. • Short circuit current flows during the time when both transistors are in ON state. • It depends on the rise or fall times of the input waveform. • It also depends on the load output capacitance. Decreases for larger output load capacitance. • The peak short circuit current occurs at the time when the transistor switching off goes from linear to saturation region. VLSI D&T Seminar

15. Short Circuit Current, isc(t) VDD - VTp V2 Volt Vi(t) Vo(t) VTn 0 Iscmaxf isc(t) Amp Time (ns) t1 t2 t3 1 0 VLSI D&T Seminar

16. Short circuit current calculation. VDD R=large isc(t) vi (t) vo(t) CL Ron tr iC(t) tf Ground VLSI D&T Seminar

17. Short Circuit Modeling • Ip(T1) = VDD2 Kp[(Vin – 1 –p )(Vout – 1)0.5(Vout – 1)2] • Ip(T2) = VDD2 0.5Kp (Vin – 1 –p )2 where T1 = t2 – t1 T2 = t3 – t2 Kp = pMOS gain factor. p = Vtp/VDD VLSI D&T Seminar

18. Short Circuit Modeling. Reference: Wang, Q. and Vrudhula, S. B. K., "On short circuit power estimation of CMOS inverters," Proc. International Conference onComputer Design (ICCD’98), Oct 1998, pp. 70-75. VLSI D&T Seminar

19. Experimental Results (Average Power Dissipation for 1000 Random Vectors) • * Sun Ultra Workstation VLSI D&T Seminar

20. A Few Observations. • If a gate has a greater fan-out , its dynamic power dissipation will increase. However the total dynamic dissipation increase will depend on the switching activity of the gate. • A gate whose input node has a greater fan-out, will have an increase in short circuit power as the input rise or fall time to that gate will be higher as observed in circuits like c432. • A gate with a bigger fan- out can increase short circuit power dissipation only if it causes an event at its fan- out gates. This phenomenon can be seen while comparing circuits c1908 and c2670. VLSI D&T Seminar

21. Experimental Results (Maximum and Minimum Power Components) VLSI D&T Seminar

22. Histogram for c7552 (1000 Random Vectors) VLSI D&T Seminar

23. Investigation of c7552 circuit • The circuit produces a large number of glitches. Almost 66% of the total events are found to be glitches. • Analysis of NAND gate #3718 showed that for a 1 to 0 transition, the gate undergoes 22 extra transitions (glitches) before settling to steady state 0. VLSI D&T Seminar

24. Ongoing Work • Estimation of clock power (power dissipated in clock trees or clock buffer circuits). • Estimation of power in sequential and scan circuits. • Spice validation of results at gate level. VLSI D&T Seminar

25. Conclusion • This work discusses the techniques used for the efficient estimation of power in CMOS circuits. • The tool successfully does a gate level logic simulation and separates different power components. • Future work involves validation of results through Spice simulation of smaller circuits. VLSI D&T Seminar

26. THANK YOU….. VLSI D&T Seminar