PCI B ASED R EAD-OUT R ECEIVER C ARD IN THE ALICE DAQ S YSTEM

1. PCIBASED READ-OUT RECEIVER CARD IN THE ALICE DAQSYSTEM W.Carena1, P.Csato2, E.Denes2, R.Divia1, K.Schossmaier1, C. Soos1, J.Sulyan2, A.Vascotto1, P.Vande Vyvre1 1CERN EP/AID, 2KFKI-RMKI (Budapest) NEC 2001 Varna, Bulgaria 12 – 18 September, 2001

2. OUTLINE • ALICE DAQ system • DDL components • DDL requirements • PCI-RORC concept • PCI-RORC development • PCI-RORC performance • Summary NEC2001, 12-18 September, 2001

3. ALICE DAQ SYSTEM NEC2001, 12-18 September, 2001

4. DDL COMPONENTS • Destination Interface Unit (DIU) • Source Interface Unit (SIU) • Physical medium • Multimode optical cable • Maximum 200m long Forward Channel Read-Out Read-out Receiver Card (RORC) Front-End Electronics (FEE) Source Interface Unit (SIU) Destination Interface Unit (DIU) Front-End Receiver Electronics Card (FEE) Backward Channel (RORC) Physical Medium DDL Hardware = Source Interface Unit + Physical Medium + Destination Interface Unit NEC2001, 12-18 September, 2001

5. DDL REQUIREMENTS • Bi-directional data transfer • 100 MB/s from the detectors • 10 MB/s to the detectors • Detected BER must be less than 10-15 • Remote control capability • FEE control • SIU control • Detailed status and error reporting • Built in test capability • JTAG BST over the link • FEE control and test NEC2001, 12-18 September, 2001

6. PCI RORC CONCEPT • Interface between the DIU and PCI local bus • 32bit/33Mhz PCI version, max. throughput 132MB/s • Direct data transfer to the PC memory • No local memory on the board • Small elasticity buffers between different clock domains • Data push architecture, PCI master operation • Data transfer with minimal software interaction • Minimize latency • Memory management • Efficient for scattered memory management • Minimize software overhead • Built-in test capability • Internal pattern generator can produce quasi-realistic data NEC2001, 12-18 September, 2001

7. PCI RORC DEVELOPMENT 1/2 pRORC firmware architecture Input Mailbox Read DMA controller Transmitter FIFO IMB Pattern Generator Memory manager and command interpreter PCI to AOL FIFO AOL interface DIU interface PCI DIU AOL to PCI FIFO Write DMA controller Receiver FIFO Output Mailbox OMB AOL – Add-on Logic NEC2001, 12-18 September, 2001

8. BA BA BA BL BL BL IDX IDX IDX BA BL IDX RFBA IDX PCI RORC DEVELOPMENT 2/2 Scattered Memory Management Free FIFO (128 entry) PC physical memory Ready FIFO BA – Base Address BL – Block Length IDX – Ready FIFO Entry Index RFBA – Ready FIFO Base Address NEC2001, 12-18 September, 2001

9. PCI RORC PERFORMANCE 1/2 • Test firmware developed to test the DMA • Fixed size block transferred (n Word) • Simple test pattern used (without data check) • Test software controls the firmware and measures the performance • Stand alone operation Base address Block Counter Base address + 4 Data buffer Base address + 4(n+1) NEC2001, 12-18 September, 2001

10. PCI RORC PERFORMANCE 2/2 • Same test firmware and software used • Additional software components • Intensive memory usage (stream_l benchmarking tool) • Intensive network usage (Gigabit Ethernet) • Intensive CPU usage (stream_l + DATE1) 1 DATE – Data Acquisition and Test Environment 2 400 KB block size NEC2001, 12-18 September, 2001

11. SUMMARY • Results: • 5 boards are available for prototyping • Software drivers for 2.2.x and 2.4.x kernels • Software library for integration with DAQ system • Future plans: • Migrate to PCI 64bit/66MHz • Implement on-board memory and pre-processing capabilities • Develop WEB-based GUI NEC2001, 12-18 September, 2001

12. NEC2001, 12-18 September, 2001

13. PCI RORC BOARD NEC2001, 12-18 September, 2001

14. DDL DIU BOARD NEC2001, 12-18 September, 2001

15. DDL SIU BOARD NEC2001, 12-18 September, 2001