Petros Oikonomakos Mark Zwolinski

1. Electronics and Computer Science Controller Self-checking in a Controller / Datapath Architecture Petros Oikonomakos Mark Zwolinski 3rd UK ACM SIGDA Workshop on EDA Southampton, UK, 11-12 September 2003 Electronic Systems Design Group University of Southampton, UK

2. Outline • Introduction • Target Architecture • Parity-based Techniques • Intrinsically Secure States • Self-checking design theory • 1/n self-checking • Conclusion

3. Introduction • Starting point : controller / datapath system, self-checking datapath [Oikonomakos et al, DATE 2003] • Goal : controller self-checking, integration with previous work • Requirements : technology independence, ease of automation (time to market), area efficiency, adherence to self-checking theory • Complete, automatically produced, controller / datapath self-checking solution!!!

4. Target Architecture • Controller / datapath architecture • Possibly several communicating FSMs • Previous work : self-checking at point A • Self-checking at point B is essential!!!

5. Per process parity-based self-checking

6. Single parity-based self-checking

7. Hardware Costs • per process parity checking : ~(NS+5×n) gates • single checker : ~NS gates NS : total number of states n : number of processes • the higher the degree of parallelism, the more the hardware savings!!!

8. Intrinsically Secure (I.S.) States

9. Exploiting I.S. States in a process • basic scheme • detects all single control signal faults • possibly little hardware saving • several multiple faults are also detected!!!

10. Per process I.S. states-based self-checking

11. Single I.S. states-based self-checking

12. First experimental results • Qrs benchmark • Target Technology Alcatel CMOS .35 VLSI

13. Self-checking design theory • modelled faults Φ • code inputs A • code outputs B • the fault-secure property • the self-testing property • the totally self-checking (TSC) property • checker structure + system operation

14. Example • Φ={all stuck-at faults} • A={01110, 01000, 00111} • B={01, 10}

15. Self-checking design theory Four vectors required to achieve the TSC goal for a parity checker (Khahbaz and McCluskey, TCOMP 1984) • 0 1 ………….. • 0 1 1 ………….. • 1 0 ………….. • 0 0 0 ………….. rows : distinct, same parity each column : exactly 2 1s and 2 0s

16. Self-exercising parity checker design taken from Tarnick, VLSI Design 1998

17. 1/n checker by Khakbaz, TCOMP 1982 • TSC for n>3 • generic • technology-independent • friendly to design automation • sometimes criticised as slow, but this does no harm here

18. Per process 1/n self-checking

19. Per process 1/n self-checking utilising I.S. states

20. Experimental results • Diffeq benchmark • Target Technology Alcatel CMOS .35 VLSI

21. Conclusion • self-checking at the raw, one-hot control signals • alternative controller self-checking schemes • datapath self-checking resource reuse (Intrinsically SecureStates) • implementation within a synthesis system, providing full datapath and controller self-checking solutions