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Full Chip Analysis

Full Chip Analysis. Chung-Kuan Cheng Computer Science and Engineering Department University of California, San Diego La Jolla, CA 92093-0114 Kuan@cs.ucsd.edu. Outlines. Introduction Circuit Level Analysis Logic Level Analysis Timing Analysis Functional Analysis Mixed Signal Analysis

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Full Chip Analysis

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  1. Full Chip Analysis Chung-Kuan Cheng Computer Science and Engineering Department University of California, San Diego La Jolla, CA 92093-0114 Kuan@cs.ucsd.edu

  2. Outlines • Introduction • Circuit Level Analysis • Logic Level Analysis • Timing Analysis • Functional Analysis • Mixed Signal Analysis • Research Directions • Conclusion

  3. I. Introduction • Trends of On-Chip Technologies • Statistics About Design Flaws • Spectrum of Analysis

  4. I.1 Trends of On-Chip Technologies System: Huge Numbers of Devices and Wires Power/Ground Distribution: Low Voltage, High Current Wires: Lateral Coupling, Fragmented Parasitics Devices: Modeling, Noise Mixed Signal Design: RF+Analog+Digital

  5. Power/Ground Distribution (ITRS) Lower V margin: Higher I & Inductance x Freq.

  6. Static Vs. Dynamic Voltage Drop Dynamic - peak current Current envelope Static- average current (n+2)T (n+1)T nT • Wire sizing can be used to control static drop • Precise de-cap insertion filters peak current spikes Courtesy of Apache

  7. Flip Chip Dynamic Effects Dynamic Static Dynamic Total Static vs. Dynamic F:MHz Vdd Ri(t) IR Ldi/dt 0.5% 1.02% 18.5 mV 17.3 mV 1.2 mV 1.8 9.9 mV 250 1.08% 2.77% 41.6 mV 12.3 mV 29.3 mV 1.5 16.2 mV 500 1.6% 5.37% 64.5 mV 28.5 mV 36 mV 1.2 750 19.3 mV 2.2% 8.0% 1.0 22 mV 38.8 mV 41.6 mV 1,000 80.4 mV Courtesy of Apache

  8. Wire-bond Dynamic Effects Dynamic Static vs. Dynamic Static Dynamic Total F:MHz Volt R i(t) Ldi/dt IR 5.7% 8.3% 150 mV 147 mV 3 mV 1.8 103 mV 133 12% 19.2% 288 mV 13 mV 275 mV 1.5 181 mV 250 16.6% 29.2% 351 mV 75 mV 276 mV 1.2 400 200 mV Courtesy of Apache

  9. Increasing System Complexity RF front end Complex converters DSP Memory Courtesy of Mentor

  10. I.2 Statistics about Design FlawsPercent of Total Flaws Fixed in IC/ASIC Designs Having Two or More Silicon Spins Collett Intl. 2000 Survey • Logical or Functional • Analog • Noise • Slow Path • Mixed-signal interface • Clock, Power/Ground • Firmware • Logical or Functional • Slow Path • Noise Collett Intl. 2001 Survey

  11. Extraction CS EE Algorithms Database Programming Circuit theory Precision I.3 Spectrum of Analysis Physics Engineering Complex, Real Discrete Math

  12. I.3 Spectrum of Analysis(flow) System Software Hardware power clock Library IP blocks Analog emulation Floorplan Architect global wires function cross talk Logic Layout freq critical paths Function Timing Circuit Anal. characterization mixed signal power noise Chip

  13. Synopsys Cadence Mentor Cadence Synopsys Axis Apache Cadence Mentor ASX Eldo Mentor Aptix Celestry Synopsys Cadence Hspice Spice IBM Nassda Iota Mentor I.3 Spectrum of Analysis(coverage) Coverage Logic: Static Timing (sign off) Logic: Functional Mixed Signal Circuit Analysis Circuit Size

  14. I.3 Spectrum of Analysis(trend) • Layout Dominated Analysis • Power/Ground, Clock • Wires • Pre-layout, Post-layout • Layout Oriented Analysis • EE + CS • EE=> CS High Complexity • CS=>EE Deep Submicron Effect • Accuracy and Efficiency

  15. II. Circuit Level Analysis • Circuit Analysis Advancement • Circuit Analysis Techniques • Examples • Tasks

  16. II.1 Circuit Analysis Advancement 1st Generation (SPICE) 2nd Generation (Fast SPICE) Next Generation (HSIM) Memory Usage Memory Usage Memory Usage Memory Usage Memory Usage Memory Usage 100M 1G Bytes Bytes 100K elements Bytes 2M elements 512M 512M Bytes Bytes 300M elements Circuit Size Circuit Size Circuit Size Circuit Size Circuit Size Circuit Size CPU Time CPU Time CPU Time CPU Time CPU Time CPU Time 100 100 hrs hrs 20 hrs 20 hrs 100K elements 2M elements 2 hrs 2 hrs 300M elements Circuit Size Circuit Size Circuit Size Circuit Size Circuit Size Circuit Size Courtesy of Nassda

  17. II.2 Circuit Analysis Techniques • Memory: Hierarchical Database • Circuit Size: Parasitic Reduction • Device Complexity: Table Model • Simulation: • Backward Euler, Trapezoidal Integration • Hierarchical Flow • Event Driven (ignoring miller effect) • Mixed Rate, Multiple step sizes (partition)

  18. II.3 Examples (HSIM) Courtesy of Nassda

  19. Speed Accuracy II.4. Tasks Input Patterns Device Mod. Convergence Hierarchy Database Event Driven Circuit Red. Matrix Solver Hierarchical Flow Integration Partition CS EE Math

  20. III. Logic Level Analysis 1.Separation of Timing and Function 2.Static Timing Analysis Algorithms, Gate Models, Path, Cross Talks 3.Functional Analysis Event Driven, Cycle Based 4.Tasks

  21. III.1 Separation of Timing and Function Function + Timing Timing Analysis Slew, RC tree cross talk High Complexity! Functional Analysis Simple timing model Input independent Input vector driven

  22. III.2 Static Timing Analysis • Algor.: Shortest and Longest Paths Search • Gate Model: • Logic: Unate, Binate Signal Propagations • Timing: functions of Input Slope and Output Load • Path Model: • Logic: False Path, Multiple Cycle Path, Cycles of Combinational Logic, Multiple Clock Frequencies • Timing: RC Tree • Cross Talks: Timing Window, ATPG • Tasks

  23. III.2.i Algor.: Path Search Longest & Shortest Paths B C Arrival Time, Slew Rate PI1 A G H J PI2 PO Required Arrival Time PI3 F E D 0->1 slew rate window 1->0 slew rate window 0->1 arrival time window 1->0 arrival time window Static Timing Analysis: Worst Case Analysis, Independent of Input Patterns

  24. 1/2 1 3 2 0/0 B C PI1 A 1 2 1 2 2 G H J PI2 PO 0/0 3 3/3 3 1 2 2 2 2 PI3 F 0/0 E D 2/4 III.2.I Algor: Path Search(cont) min/max

  25. III.2.I Algor: Path Search(cont) aminj, amaxj dji amini,amaxi amini=minj aminj+dji amaxi=maxj amaxj+dji

  26. 1/2 4/5 6/7 1 3 2 0/0 B C PI1 A 1 2 1 2 2 G H J PI2 PO 0/0 3 3/3 3 6/10 8/12 1 4/4 2 2 2 2 PI3 F 0/0 E D 6/8 2/4 4/6 III.2i Algor.: Path Search Longest: PI2,G,F,E,D,J,PO Shortest: PI2,G,H,J,PO min/max

  27. a a a y y y III.2.ii Gate Logic Model: Unate & Binate Signals NAND BDD Unateness: a 0->1 => y 1->0 Check unateness based on BDD XNOR Binateness: a 0->1 => y 0->1 & 1->0

  28. a y Ceff III.2.ii Gate Timing Model Interconnect Slew rate of a Slew rate of a Delay of y Slew rate of y Ceff Ceff

  29. y c4 c8 4 bit adder c0 4 bit adder z p[0,3] Carry skip adder III.2.iii Path Logic Model: False Path 1 C0=1 1011 0100 1111 + P[0:3]=1 10000 Z=1

  30. y c4 c8 4 bit adder c0 4 bit adder z p[0,3] Carry skip adder III.2.iii Path Logic Model: False Path False path: c0->y->c4 ->c8 Assumption: z->c4 ->c8 derives results faster If we erase all false paths, we can identify the true critical paths and the corresponding input patterns

  31. 17,24 a e 10 3 3,10 7,14 4 c d 16 2 10 f b III.2.iii Path Logic Model: False Path red+red=>red red+blue=>blue blue +blue=>blue False path b->c->d->e

  32. WCN: worst-case noise: Delay & Glitch Noise with maximum pulse height Fixed circuit structure and parameters Fixed transition time of input signals Variable arrival time of input signals WCN III.2.iv Cross Talk

  33. A1 P1 A2 P2 A3 P3 A4 P4 V0 P5 III.2.iv Cross Talk: Timing Window Aggressor / Victim Input Victim Output Aligned arrival time Skewed peak noise

  34. A1 P1 A2 P2 A3 P3 A4 P4 V0 P5 Sweep line III.2.iv Cross Talk: Timing Window Aggressor / Victim Input Victim Output Skewed arrival time Aligned peak noise Aggressor Alignment WITHOUT Timing Constraints

  35. A1 A2 A3 A4 V0 Sweep Line III.2.iv Cross Talk: Timing Window Aggressor / Victim Input Victim Output P1 P2 P5 Aggressor Alignment WITH Timing Constraints

  36. Latest arrival time Earliest peak noise occurring time III.2.iv Cross Talk: Effective Timing Window Timing window for aggressor input Timing window for victim output Earliest arrivaltime Latest peak noise occurring time

  37. Old Sweep Line New Sweep Line Aggressor Alignment with Timing Constraints -- Reformulation New Sweep Line A1 A2 A3 A4 V0 (a) Original timing window (c) Expanded timing window (b) Shifted timing window

  38. Speed Accuracy CS EE III.2.v Tasks Path model: special cases Gate model: power, noise Path model: RCLK reduction Path search in hierarchy Cross talk ATPG Timing window+pattern Math

  39. III.3 Logic Level: Functional Analysis • Functional Analysis Techniques • Event Driven Analysis • Cycle Based Analysis • Tasks

  40. III.3.i Functional Analysis Techniques • Event Driven Simulation • VCS, Verilog-XL, VSS, ModelSim • Cycle Based Simulation • Frontline, Speedsim, Cyclone • Domain Specific Simulation • SPW, COSSAP

  41. III.3.ii Event Driven Analysis • Event Wheel • Maintains schedules of events • Enables sub-cycle timing • Advantages • Timing accuracy • Good Debug Capability • Handles asynchronous • Disadvantages • Performance

  42. III.3.iii Cycle Based Analysis • RTL Description • All gates evaluated every cycle • Schedule is determined at compile time • No timing • No asynchronous feedback, latches • Regression Phase • High Performance • High Capacity

  43. Speed Accuracy CS EE III.3.iv Tasks Hardware acceleration Dynamic timing model Pattern generation coverage Math

  44. Complex Analog Custom Logic & Mixed-Signal RF front-end Fast SPICE RF Simulator Traditional SPICE Analog IP VHDL-AMS Verilog-AMS Embedded Memories DSP Hierarchical Fast SPICE HDL VHDL/Verilog Single-Kernel simulator for full-chip SoC Verification IV. Mixed Signal Analysis Courtesy of Mentor

  45. D/A D/A A/D A/D IV. Mixed Signal Analysis: Interface Analog Digital Rise, Fall Time Rise, Fall Resistance Analog Signal Threshold Detector 0, 1, X

  46. VHDL-AMS Spice C Spice VHDL-AMS VHDL Verilog VHDL Verilog Verilog-A Verilog-A Verilog-A Verilog Verilog-AMS VHDL VHDL-AMS Spice Spice VHDL-AMS Spice C Mixed Signal: Mixed Languages • Single Kernel Architecture • Single Netlist Hierarchy • Automatic D/A and A/D converter insertion Courtesy of Mentor

  47. Speed Accuracy CS EE IV. Tasks Language RF, Analog, Power, Noise, Convergence Interface Compiler Partition Math

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