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Status of TDCpix full chip assembly

Status of TDCpix full chip assembly. NA62 – GTK WG meeting. Sandro Bonacini. Full chip floorplan. Pixel matrix. 20.400x12.030 sq.mm PRELIMINARY Floorplan work started June 2012 Top assembly done in Virtuoso “South bank” P&R in Encounter Size: ~4.8 mm. “South bank”.

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Status of TDCpix full chip assembly

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  1. Status of TDCpix full chip assembly NA62 – GTK WG meeting Sandro Bonacini

  2. Full chip floorplan Pixel matrix • 20.400x12.030 sq.mm • PRELIMINARY • Floorplan work started • June 2012 • Top assembly done in Virtuoso • “South bank” P&R in Encounter • Size: ~4.8 mm “South bank”

  3. South bank floorplan • Assembly of TDC, qchip, bandgaps, serializer/PLL, I/O pads & power • Pad placement is preliminary • 158 south + 4 west + 4 east • 22 staggered power pads TDC (x20) qchip (x4) config space, DLL clock & cal. fanout BGs Serializer & PLLs BG Staggered pads Staggered pads

  4. Power distribution • Regular 600-um-pitch power lines in matrix • Sparse 60-um lines in pad ring

  5. Power distribution • SW corner • I/O pads • Power/ground pads • “Pitch adapter” • Dense connections in horizontal and vertical power lines BG Staggered pads

  6. Status • Completed • Floorplan • Power planning / distribution • Next steps • “South bank” • Place & route, DFM, chip finishing • No major showstoppers • Verification (DRC, LVS) • … might need some iterations at this stage. • Complex power distribution, global nets, … • Final chip assembly

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