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Delay Defect Characteristics and Testing Strategies

Delay Defect Characteristics and Testing Strategies. Kee Sup Kim, Subhasish Mitra, and Paul G.Ryan Design&Test 2003. Introduction. A timing failure is case that circuit can’t operate correctly at the specified speed setup time violation hold time violation This paper discusses

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Delay Defect Characteristics and Testing Strategies

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  1. Delay Defect Characteristics and Testing Strategies Kee Sup Kim, Subhasish Mitra, and Paul G.Ryan Design&Test 2003

  2. Introduction • A timing failure is case that circuit can’t operate correctly at the specified speed • setup time violation • hold time violation • This paper discusses • delay defect characteristic • impact on IC quality • testing strategy

  3. What Significance of Delay Defect? • Output response for 30% to 35% of defective parts depend on the test speed. (VTS02) • Delay defects have typically represented 1% to 5% of the total defect population observed. (Intel) • At-speed functional testing is cost prohibitive • on-chip clock source • ATE cost/test pattern generation • low voltage testing

  4. Delay Defect Classification • Gross defects: cause errors at any speed • Delay defects: affect the fmax only • Systematic delay defect (process or intrinsic defect) • Broad impact on the unit • Random defect (point or spot defect) • At single location and several paths

  5. Timing Failure due to Process Variation • Probability distribution for path delay

  6. Solutions to Process Timing Failure • Choice of product’s operating frequency • economic tradeoff • Speed binning: • to distinguish faster parts to be sold at a higher price • Over-design: • increase the die size, power, and packages cost

  7. Characteristic of Speed Failure • First-fail data from microprocessor (.18m) • Process variation -> critical path • Random defect -> any locations

  8. Distinguishing of Defects • Two complementary techniques to differentiate random defects and process variation • Signature-based approach • analyze the number of units sharing each fail signature • random defects on critical path • Frequency distribution technique • Analyze the fmax data for all units sharing a common signature

  9. Histogram of fmax • Normal process variation results in fmax values with a Gaussian distribution

  10. Delay Testing Techniques • Some delay defect can be detected by process monitor • ring oscillators • trees of NAND gates with controlled delays • Boolean testing at some clock frequency • test pattern generation? • at what clock frequency?

  11. Test Pattern for Systematic Delay Defect • Systematic delay problem caused by process variation will affect several paths including the critical path • Functional test • patterns are manually written by designers • Advantage • it can be exercised in the system • Disadvantage • difficult and cost a lot of time

  12. Test Pattern for Random Delay Defect • Comparing to the systematic defects, additional test patterns covering the entire design are required • Using the path delay fault model • complexity issue • Using the transition-fault model • total number of transition fault • 100% fault coverage • EDA tool support • without timing analysis

  13. Impact of Inaccurate Timing analysis • Static timing analysis/dynamic timing analysis • gate delay, interconnection delay • Many physical factor affect the accuracy • voltage, temperature, skew, cross-talk, … • For large designs, the center and the edge may exhibit different speed • A fault model for delay defect must not be critically dependent on accurate timing analysis

  14. Limitation of Transition Fault Model • Which path excites a transition fault or propagates the fault effect does not consider • If the fault effect propagates from the fault site along a very short path with a lot time slack • ATPG issue?

  15. Test Pattern with Scan-based Test • Approaches to generating a pair of test patterns with scan: • One memory element • Skewed-load or launch-on-last-shift • Double-pulse or launch-on-capture • Two memory element • LSSD • False path problem • paths is detected but cannot exercised during normal operations • yield-loss

  16. Launch-on-Shift Scan • V2 is shifted version of V1 (un-testable fault) • SE routing is critical • ATPG is easy

  17. Launch-on-Capture • SE routing is easy • ATPG is more complex

  18. Effectiveness of TF Testing • ASIC1 (0.18m) with 800K gates from LSI Logic • IEEE D&T 2003

  19. Effectiveness of TF Testing (cont.) • Venn diagram of test results Launch-on-capture Total 245 units 80 19 74 16 3 53 Launch-on-shift 0 At-speed functional

  20. More Issues? • Multiple clock domains • High performance application • How fast to apply clock • Most solutions increase the complexity of ATPG

  21. Conclusion • Overdesign cannot guarantee all parts pass the delay defect screening • For systematic delay defects • process monitor • critical-paths delay testing • For random defects • transition-fault testing is necessary • Test compression is considered due to test economics

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