Key Results - Verification

1. Key Results - Verification • Developed and released ATPG-based SAT solvers for circuits(Univ. of California, Santa Barbara) • Integrating structural ATPG and SAT techniques with new conflict learning • CSAT: Fast combinational solver (released on March 2003) • Demonstrated 10-100X speedup over state-of-the-art SAT solvers on industrial test cases (reported by Intel and Calypto) • Has been integrated into Intel’s FV verification system and a startup’s verification engine • Publications: DATE2003 and DAC2003 • Satori2: Fast sequential solver (released on Dec. 2003) • Demonstrated 10X-200X speedup over a commercial, sequential ATPG engine on public benchmark circuits • Publications: ICCAD2003, HLDVT2003 and ASPDAC2004

2. ATPG/Pattern Selection Diagnosis Critical Path Selection Defect Injection & Simulation Path Filtering Dynamic Timing Simulator Static Timing Analysis Statistical Timing Analysis Framework (Cell-based characterization) Key Results - Testing A new Statistical Delay Testing and Diagnosis framework consisting of five major components (UCSB): • Statistical timing analysis • Statistical critical path selection [DAC’02,ICCAD’02] • Selecting statistical long & true paths whose tests maximize detection of parametric failures • Path coverage metric [ASPDAC’03] • Estimating the quality of a path set • Selection/Generation of high quality tests for target paths [ITC’01][DATE 2004] • Identifying tests that activate longer delay along the target path • Delay fault diagnosis based on statistical timing model [DATE’03, VTS’03, DAC’03] • Ref: Krstic, Wang, Cheng,& Abadir, DATE’03–Best Paper Award in Test

3. Key Results - Testing • On-Chip Jitter Extraction for Bit-Error-Rate (BER) Testing of Multi-GHz Signal (UCSB) • Using on-chip, single-shot measurement unit to sample signal periods for spectral analysis • Demonstrated, through simulation, accurate extraction of multiple sinusoids and random jitter components for a 3GHz signal • Publications: ASPDAC2004 and DATE2004