High-Speed , High-Resolution , Radiation-Tolerant SAR ADC for Particle Physics Experiments

1. High-Speed, High-Resolution, Radiation-Tolerant SAR ADC for ParticlePhysicsExperiments Yuan Zhou1, Hongda Xu1, Yun Chiu1 Datao Gong2, Tiankuan Liu2, Jingbo Ye2 1University of Texas at Dallas, Richardson, TX, USA 2Southern Methodist University, Dallas, TX, USA

2. Outline • Introduction • Recent Advances in SAR ADCs • Our Recent 12-bit SAR ADC Works • 45-MS/s SAR Prototype (0.13μm, 2010) • 160-MS/s SAR Prototype (40nm, 2014) • Total Ionization Dose (TID) Results (40nm) • Summary

3. Outline • Introduction • Recent Advances in SAR ADCs • Our Recent 12-bit SAR ADC Works • 45-MS/s SAR Prototype (0.13μm, 2010) • 160-MS/s SAR Prototype (40nm, 2014) • Total Ionization Dose (TID) Results (40nm) • Summary

4. ADC in Phase-II LAr Readout FEB • High resolution: 12-14 bits • High speed: 40-80 MS/s • Low power, low area • Radiation tolerant Potential Phase-II Upgrade FEB (On detector) Detector Output Signal Analog Shaper Preamp MUX & Serializer To Back-end ADC Optical Links

5. Architecture Choice: SAR vs. Pipeline Pipeline SAR • Pipelined ADC: High-gain residue amplifier hard to scale w/ process • SAR ADC: low-power, low-area is a strong candidate for Phase-II

6. Outline • Introduction • Recent Advances in SAR ADCs • Our Recent 12-bit SAR ADC Works • 45-MS/s SAR Prototype (0.13μm, 2010) • 160-MS/s SAR Prototype (40nm, 2014) • Total Ionization Dose (TID) Results (40nm) • Summary

7. SAR and Pipelined ADCs (<2014) Pipeline ADC Best design Constant Performance Performance = 2∙BW∙3ENOB X∙Y = Power 10W Constant-Power Hyperbola Constant Efficiency Performance Efficiency 1W SAR ADC Power 10μW 100μW 100mW 1mW 10mW Efficiency = Power/(2∙BW∙3ENOB) ISSCC & VLSI data

8. Outline • Introduction • Recent Advances in SAR ADCs • Our Recent 12-bit SAR ADC Works • 45-MS/s SAR Prototype (0.13μm, 2010) • 160-MS/s SAR Prototype (40nm, 2014) • Total Ionization Dose (TID) Results (40nm) • Summary

9. 12-bit, 45-MS/s, 0.13-μm CMOS ADC Sub-binary DAC ODC Redundancy CAL

10. Sub-Binary DAC and Redundancy Binary Super-binary Sub-binary • Built-in redundancy helps combat dynamic conversion errors (DAC mismatch, comparator, DAC settling, even SEU) • Redundancy is also needed for digital claibration

11. Offset Double Conversion (ODC) Digital Post-Processing • ODC is implemented in DAC w/ a small cap

12. How to determine Bit Weights? Is the transfer curve shift-invariant?

13. How to determine Bit Weights? Is the transfer curve shift-invariant?

14. How to determine Bit Weights? Is the transfer curve shift-invariant?

15. How to determine Bit Weights? • Shift-invariant ONLY when the transfer curve is completely linear! • Non-constant difference b/t D+ and D− reveals bit weight information

16. 12-bit, 45-MS/s, 0.13-μm CMOS ADC Sub-binary DAC ODC Die size: 0.06 mm2 • 12 b, 45 MS/s in FG mode • 3-mW power (36.3 fJ/step) • Most read JSSC article Nov. 2011

17. Measured ADC Spectra (BG Mode) SNDR = 60.2dB SFDR = 66.4dB THD = -61.7dB SNDR = 70.7dB SFDR = 94.6dB THD = -89.1dB After Cal. Before Cal.

18. Comparison with 12-bit ADCs (@ time of publication) 46 fJ/step @ 22.5 MS/s 31 fJ/step @ 45 MS/s 0.06 mm2 Total Power: 3.0 mW

19. Outline • Introduction • Recent Advances in SAR ADCs • Our Recent 12-bit SAR ADC Works • 45-MS/s SAR Prototype (0.13μm, 2010) • 160-MS/s SAR Prototype (40nm, 2014) • Total Ionization Dose (TID) Results (40nm) • Summary

20. 12-bit, 160-MS/s, 40-nmCMOS ADC • (5b + 8b) synchronous two-step pipelined SAR architecture • First-stage capacitor weights identified w/ opportunistic DAC dither

21. Subranging, Swing, and Linearity 1-bit redundancy tolerates offset • Smaller output swing for residue amplifier • Compensated by 2nd stage SAR ADC • Increased resolution (7 bit  8 bit) • Scaled reference voltage (Vref  0.5Vref)

22. Simple Residue Amplifier • Two-stage amplifier provides ~ 30-dB gain • Gain error is lumped into bit weights and calibrated

23. Second-Stage SAR ADC • Reference voltage is effectively halved • Minimal loading determined by kT/C noise

24. Die Photo 300μm Clock & PN Gen. Sub- ADC3 Sub- ADC1 Sub- ADC2 Sub- ADC4 Sub- ADC5 139μm Integrator + DAC MDAC2 MDAC3 MDAC1 MDAC4 40-nm digital CMOS process (die size = 0.042 mm2)

25. Measured ADC Dynamic Performance fs = 160MHz after cal. fin = 25MHz after cal. fNyquist=80MHz fs=160MHz fin [MHz] fs [MHz]

26. Power Breakdown (VLSI’14 Version) Analog 1.1V 2.8mW (53.6%) • Total power is ~ 5 mWat 160-MS/s operation

27. ADC PE Chart Revisited 12b,160MS/s 5mW Best design Performance 10W 1W 10μW 100μW 1mW 10mW 100mW Efficiency ISSCC & VLSI data

28. Outline • Introduction • Recent Advances in SAR ADCs • Our Recent 12-bit SAR ADC Works • 45-MS/s SAR Prototype (0.13μm, 2010) • 160-MS/s SAR Prototype (40nm, 2014) • Total Ionization Dose (TID) Results (40nm) • Summary

29. TID Test of 40-nm CMOS SAR ADC • DUT under X-ray radiation when powered up w/ clock input. • ADC performance (e.g., SNDR, SFDR, power, etc.) measured after irradiation is complete.

30. Measured SNDR and SFDR @ 80 MS/s

31. Measured SNDR and SFDR @ 160 MS/s

32. Annealing (fs= 80 MS/s)

33. Annealing (fs= 160 MS/s)

34. Measured ADC Power

35. Outline • Introduction • Recent Advances in SAR ADCs • Our Recent 12-bit SAR ADC Works • 45-MS/s SAR Prototype (0.13μm, 2010) • 160-MS/s SAR Prototype (40nm, 2014) • Total Ionization Dose (TID) Results (40nm) • Summary

36. Summary • High-resolution and high-speed SAR ADC is a strong candidate to meet the stringent requirements in HEP experiments • The preliminary irradiation test (TID) results further highlight the feasibility of SAR ADC in deeply scaled CMOS processes for HEP applications • Low power and small die size of SAR present great potentials for spatial redundancy technique to be employed in single-event upset (SEU) treatment Thank you for your attendance!