1 / 8

11M

11M. Neil D’Cunha. Everything about Asynchronus CPU's. - That you never cared about or ever wanted to know. Name is a misnomer There are still sequential parts Just no global or circuit wide clocks Each module clocks the next module Self Timed or Self Clocked is a better name

jasper
Download Presentation

11M

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 11M Neil D’Cunha

  2. Everything about Asynchronus CPU's - That you never cared about or ever wanted to know • Name is a misnomer • There are still sequential parts • Just no global or circuit wide clocks • Each module clocks the next module • Self Timed or Self Clocked is a better name • This is called a handshake protocol

  3. My Handshake Protocol • Initial attempt proved to be difficult to simulate • Active Qn stage would clock Qn+1 stage • Qn+1 would deactivate Qn • Qn+1 would become Qn • Problem: How to start this thing? • Next attempt was to have a linear chain • Each stage would clock the next stage • Final stage would deactivate the next all stages • Code proved to be unsynthesizeable • Replaced with an FSM that replicated handshaking

  4. Model of the my Asynchronous CPU

  5. Operation • Start (stage 0) is always forced high to simulate a valid • Every state is in the "invalid" state • Each stage • Checks if previous stage is valid • Does it's job • Becomes valid • Weird result - I created a 7 stage pipeline CPU • Slight modifications to the code • Control Registers • Instruction Registers

  6. My CPU in more detail • Based off the PicoBlaze CPU for Xlinix FPGA's • Tried to recreate similar functionality • ALU has less functionality • 16 Registers in Total • 8 User Registers • 8 System Registers - PC, RA, SP • Most instructions can use a register or immediate value • Very scalable - used parameterized VHDL code

  7. No Instruction Assembly Machine Code 1 Addition ADD $D $F $S 0000 $D [$F or O] [$S or O] M 2 Subtract SUB $D $F $S 0001 $D [$F or O] [$S or O] M 3 AND AND $D $F $S 0010 $D [$F or O] [$S or O] M 4 OR OR $D $F $S 0011 $D [$F or O] [$S or O] M 5 Load Upper LUR $D HH M 0100 $D HH M 6 Load Lower LLR $D HH M 0101 $D HH M 7 Load Word LM $D $F [$S or O] M 0110 $D $F [$S or O] M 8 Store Word SM $D $F [$S or O] M 0111 $D $F [$S or O] M 9 Set Equal SEQ $F [$S or O] M 1000 --- $F [$S or O] M 10 Set Unequal SNE $F [$S or O] M 1001 --- $F [$S or O] M 11 Set Lesser SLT $F [$S or O] M 1010 --- $F [$S or O] M 12 Set Greater SGT $F [$S or O] M 1011 --- $F [$S or O] M 13 Input INP $D [$S or O] 1100 $D --- [$S or O] M 14 Output OUT $D [$F or O] 1100 --- $F [$S or O] M 15 Jump JMP A [$F or OO] M 1110 A [$F or OO] M 16 Halt HLT 1111 XXX XXX XXX XXX Instruction Set Architecture

  8. Questions?

More Related