1 / 15

Presenter : Ching -Hua Huang

National Sun Yat-sen University Embedded System Laboratory. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation Citation : 15 Adir , A ., Copty , S. ;  Landa , S. ;  Nahir , A. ;  Shurek , G. ;  Ziv , A. ;  Meissner , C. ; Schumann, J.

jasper
Download Presentation

Presenter : Ching -Hua Huang

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. National Sun Yat-sen University Embedded System Laboratory A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation Citation : 15 Adir, A.,Copty, S. ; Landa, S. ; Nahir, A. ; Shurek, G. ; Ziv, A. ; Meissner, C. ; Schumann, J. IBM Res., Haifa, Israel  Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011 Presenter :Ching-Hua Huang

  2. Abstract 2 The growing importance of post-silicon validation in ensuring functional correctness of high-end designs increases the need for synergy between the pre-silicon verification and post-silicon validation. We propose a unified functional verification methodology for the pre- and post-silicon domains. This methodology is based on a common verification plan and similar languages for test-templates and coverage models. Implementation of the methodology requires a user-directablestimuli generation tool for the post-silicon domain. We analyze the requirements for such a tool and the differences between it and its pre-silicon counterpart. Based on these requirements, we implemented a tool called Threadmill and used it in the verification of the IBM POWER7 processor chip with encouraging results.

  3. What’s the problem ? • Why using Post-silicon validation? • Reasoning • The size and complexity of modern hardware systems • Sunk costs • Benefits • Tests are executed directly on manufactured silicon • In the past • Validating electrical aspects • Diagnosing systematic manufacturing defects • Today • Functional validation • Challenges • Limited internal observability • Difficult to modify the manufactured chips

  4. What’s the problem? (Cont.) 4 • The growing importance of post-silicon validation • High-end designs increases the need for synergy between the pre-silicon verification and post-silicon validation. • Propose a unified methodology to building a bridge allowing easier integration between the domains. • Difference between Pre- and Post-silicon domains • Pre-silicon platforms • Software simulators and hardware acceleration • Support detailed level of observability • Post-silicon platforms • Provide significantly higher execution speeds • The verification tools need to be adjusted for the best utilization of available speed

  5. Introduction Pre-silicon verification V.S. Post-silicon validation

  6. Related Work [1] Functional verification Implementation on the modern hardware systems is a mammoth task [2] Post-silicon methodology [14] GenesysPro [13] Threadmill Post-silicon validation is not a new idea, but very little is published on post-silicon verification methodologies. The tool that implemented the proposed methodology IBM’s well-established test generation tool for the functional verification [3-7] Most research in post-silicon validation Unified Verification Methodology Checking and debugging capabilities of the silicon platforms [This paper]

  7. Pre-silicon stimuli generation • Motivation • According to the user’s specifications, it can provide • Desired scenarios • High-quality test cases • Scenario specifications – test-templates • Test templatethat defines a scenario (on the left) and a test generated from this template (on the right). • GenesysPro-IBM’s well-established test generation tool • Functional verification of processors • The generated test cases • Must be valid to the processor’s architecture • Be different from each other as much as possible

  8. Pre-silicon stimuli generation(Cont.) Test Template Test case Test Generator Test case Simulation Test case Model of the Architecture Reference Model Testing knowledge • Testing knowledge • Defines the interesting verifications events • Register dependency • Memory collisions • Employs a reference model • Simulating on it every generated instruction

  9. Post-silicon stimuli generation • The first important characteristic • long loadingand Initialization time • Exercisers - Aself-contained solution • Generates the test-cases • Runs test-cases • Checking • It a good post-silicon solution • Only loaded once on the DUV • Problem • Simulation speed • Spend less effort in generating precise interesting scenarios • Increase in number of tests generated • Low observability • Overcome this problem by the acceleration platform

  10. A unified verification methodology • A key ingredient for the success of such methodology • Providing common languagesfor the pre- and post-silicon • Test specification, progress measure, etc. • This verification methodology • Leverages three different platforms: • Simulation, Acceleration and Silicon • Requires three major components: • A verificationplan • Directablestimuli generators suited to each platform • Functional coverage models • Identifies gaps in the implementation of the plan

  11. Threadmill Test Template Builder Accelerator Testing knowledge Silicon Model of the Architecture • Threadmill was developed to enable the unified methodology • To support a verification process by a verification plan • To guide the exerciser through test-templates • Execution process starts with a builder application • Convert the data incorporated in the test-template • The architectural model into data structures that are then embedded into the exerciser image

  12. Threadmill (Cont.) • Exerciser image is composed of three major components • Athin, OS-like layer of basic services • A representation of the test-template, architectural model, and system configuration description • Fixed code that is responsible for the exercising

  13. Before the experiment 13 • I think this paper will show the performance of Threadmill • Because it is the exercise which developed enable the unified methodology

  14. Experimental results 14 • IBM’s POWER7 processor • Implements the 64-bit IBM Power Architecture • POWER7 chip incorporates eight SMT processor cores with three levels of caches, memory and I/O controllers and other support and management logic • POWER7 Coverage results • unit simulation • core simulation • EoA : Exercisers on Accelerators • Fetch unit (IFU) and sequencing unit (ISU) • EoAis almost similar to the core simulation

  15. Conclusions and My comments • Conclusions • Random stimuli generator that is controlled via test-templates • The benefits of Threadmill • Increased synergy between the two domains • Using a directablegenerator in post-silicon validation • Incorporate more testing knowledge • Improve Threadmill to create interesting verification event • My comments • For me, there are many new information and ideas in this paper. • I still confused in some concept of this paper. • I will read more reference about this area.

More Related