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Realising the BIS

Explore the design and functionality of the Beam Interlock System at LHC, covering system architecture, permit loops, controllers, interfaces, and more. Learn about the electrical architecture, user systems, and critical functions of the BIS.

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Realising the BIS

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  1. Realising the BIS 1. Beam Interlock System Overview • Basic Description • Electrical Architecture 2. Realisation • Architecture • Beam Permit Loops • Beam Interlock Controllers • User Interfaces • RS485 signals LHC Beam Interlock System

  2. Fundamental Principles BNL / DESY systems used as a basis Beam Interlock System Proposed 2001 System architecture Basic development Tested in TI8 AUTUMN 2003 2002-2003 Current Loops Fibre Optic ‘Permit Loops’ Masking Tested in TI8 AUTUMN 2004 2004 Testing in SPS AUTUMN 2005 Dependability & EMC Programmable Logic 2005 SPS, CNGS, Sector 7-8 Installation & Commissioning 2006 BIS 2006 Remaining LHC Installation & Commissioning 2007 LHC Beam Interlock System

  3. Design Specification LHC, SPS, CNGS etc. • A CERN-wide generic Beam Interlock System • Fast • Safe • High Test Coverage • Maintainable • Monitorable • Cost Effective • Deterministic ~100μs over 28km Requesting Beam Dump = SIL 3 On startup – ‘As Good As New’ Low repair time Self-Diagnosing Provides first Post Mortem info Protects $$$ but need not be $$$ Know what it’s going to do & when LHC Beam Interlock System

  4. Function BIS 153 User Systems distributed over 28kms Both-Beam LHC has 2 Beams Some User Systems give simultaneous permit Others give independent permit Beam-1 Beam-2 LHC Beam Interlock System

  5. Types of User In LHC, BIS forms a transparent layer from User System to Beam Dump LHC Beam Interlock System

  6. Types of User In LHC, BIS forms a transparent layer from User System to Beam Dump LHC Beam Interlock System

  7. Types of User In LHC, BIS forms a transparent layer from User System to Beam Dump LHC Beam Interlock System

  8. Beam Permit Loops & BICs Beam Dump Beam-1andBeam-2 4 fibre-optic channels from Point 6 1 clockwise & 1 anticlockwise for each Beam • 10MHz Square wave generated at IP6 • Signal can be cutby any Controller • Signal can be monitoredby any Controller When any of the four 10MHz signals are absent at IP6, BEAM DUMP! Beam-1 / Beam-2 areIndependent! Beam Interlock Controllers (BIC) 16 BICs per beam - Two at each Insertion Point Up to 20User Systems per BIC 6 x Beam-1 8 x Both-Beam 6 x Beam-2 LHC Beam Interlock System

  9. LHC Dual-Controller Block Diagram LHC Beam Interlock System

  10. LHC Dual-Controller Block Diagram LHC Beam Interlock System

  11. LHC Dual-Controller Block Diagram BEAM_PERMIT_STATUS was renamed to BEAM_PERMIT_INFO in 2006 LHC Beam Interlock System

  12. Realising the BIS 1. Beam Interlock System Overview • Basic Description • Electrical Architecture 2. Realisation • Architecture • Beam Permit Loops • Beam Interlock Controllers • User Interfaces • RS485 signals LHC Beam Interlock System

  13. Electrical Architecture User System 2U Chassis (CIBU) VME Chassis LHC Beam Interlock System

  14. Permit Loops The backbone of each BIS is the beam permit loop Controllers give a LOCAL_BEAM_PERMIT (if all USER_PERMITs are TRUE) LOCAL_BEAM_PERMIT controls a switch frequency passes through loop, BEAM_PERMIT = TRUE if it’s at the end There are a pair of loops, A = anticlockwise B = clockwise LHC Beam Interlock System

  15. Controller Design The critical and non-critical functions are carried out seperately AND = Matrix CPLDs (one for A, another for B) LHC Beam Interlock System

  16. Controller Design Critical Functions The rest is non-critical LHC Beam Interlock System

  17. Controllers Have simple tasks: -take USER_PERMIT and derive LOCAL_BEAM_PERMIT LOCAL_BEAM_PERMIT: -open and closes beam permit loops -is output differentially (tree structure) Make BEAM_PERMIT_INFO by detecting the loop frequency -record a HISTORY BUFFER -Allow TEST and MONITOR of the system to be carried out. BIC is actually several boards… CIBM – Master (carries out critical functions) CIBT – Test board (Test and Monitor) CIBPx and CIBEx – Wiring boards, passive, linking everything A single VME chassis has a pair of controllers… SPS or LHC?? Critical Functions LHC Beam Interlock System

  18. LHC-type controllers LHC has two controllers in a single VME chassis, one for Beam-1 the other for Beam-2 LHC Beam Interlock System

  19. SPS-type controllers SPS has two controllers in a single VME chassis – working independently Same hardware – different routing! LHC Beam Interlock System

  20. CIBU – User Interface LHC Beam Interlock System

  21. More details… See the upcoming presentations for more info  LHC Beam Interlock System

  22. Design Rules A completely separate from B • No common point of failure • A and B matrices are different hardware, written by different engineers Matrices • Matrices Simple and Deterministic • Matrices 100% testable Dependability • Using proven components • Can test BIS As Good As New, on demand • Spare capacity in the chassis has been used to make TMR or Hot redundancy • Mature products, good manufacturers. LHC Beam Interlock System

  23. Fail Safe RS485 Links - >-7 and <12 - LHC Beam Interlock System

  24. Manchester Signals Simple Encoder and Decoder, BER is unimportant. TEST data is repeated, two successive receptions must be coherent to activate a test – no serialised comms are time critical  LHC Beam Interlock System

  25. Basic Frequencies LHC Beam Interlock System

  26. Response Time <100us <80us <7us <6us <2us <2us Extremely pessimistic = 97us almost exactly matching specification LHC Beam Interlock System

  27. FIN LHC Beam Interlock System

  28. System Locations Designed to protect CERN high energy accelerators = SPS / LHC / INJ / EXT LHC Beam Interlock System

  29. Ring versus Tree In the LHC & SPS the BIS are ‘Rings’ where each User System connects ‘directly’ to the Beam Dumping System through the BIS… Extraction and Injection BIS are ‘Trees’ where User Systems are grouped, and a Master BIC controls Beam Transfer… LHC Beam Interlock System

  30. Note about Ring versus Tree.. • Ring • BEAM_PERMIT_INFO relevant • BEAM_PERMIT_INFO used to inhibit a TEST mode • Has a BEAM_PERMIT active for several hours • Unavailability is a serious issue • Tree • Users don’t care about BEAM_PERMIT_INFO • Has a BEAM_PERMIT active for some milliseconds • Is formed by using the LOCAL_BEAM_PERMIT output of controllers • A missed extraction / injection is not the end of the world • More effective use of VME chassis has allowed a pair of controllers to be implemented in the same chassis. • In LHC one controller for Beam-1 the other for Beam-2 • In other areas (referred to as SPS) a pair of independent controllers LHC Beam Interlock System

  31. Sockets are coded B1 /= B2 LHC Beam Interlock System

  32. CIBM - Master LHC Beam Interlock System

  33. CIBT – Test and Monitor LHC Beam Interlock System

  34. Special Functions The LOCAL_BEAM_PERMIT is output in differential RS485 from each controller It can be used as a regular USER_PERMIT LHC Controllers LATCH once they have transitioned from TRUE to FALSE Safe Beam Flag is input to each controller, allowing a certain section of users to be MASKED MASK partition is defined in hardware LHC Beam Interlock System

  35. Design Rules Critical signals are active low. Routing V+ to unused pins can make a fail safe LHC Beam Interlock System

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