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GCT Leaf Card

GCT Leaf Card. Overview. Based on existing double PMC board Satellite processor prototype Utilizes VirtexII and discrete SERDES Currently in use for jet finder algorithm development Modified design will use V2Pro Embedded SERDES (Rocket I/O) Commercial multi channel optical links

jennifer-rodriquez
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GCT Leaf Card

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  1. GCT Leaf Card

  2. Overview • Based on existing double PMC board • Satellite processor prototype • Utilizes VirtexII and discrete SERDES • Currently in use for jet finder algorithm development • Modified design will use V2Pro • Embedded SERDES (Rocket I/O) • Commercial multi channel optical links • Eight boards used for complete system • Six jet, two electron

  3. System Implementation (Jet) • Data input • Accepts data from 3 RCT crates • 32 serial links at 1.6Gbps • 24 for jet data • Shares data with neighboring leaf • Data flows in one direction • Processing • Two Xilinx Virtex2Pro FPGAs • Virtex4FX devices not available yet • XC2VP70FF1513C • Three jet finders total

  4. System Implementation (electron) • Data Input • Accepts data from 9 RCT crates • No sharing required • Processing • Two Xilinx Virtex2Pro FPGAs • XC2VP501513C • Easily handles requirements • Re-use of hardware less expensive than new design

  5. Block diagram 1.6Gbps links 12 channel optical links 12 4 4 12 XC2VP70FF1513C XC2VP701513C 160 pins 80 LVDS pairs 200 pins 40MHz DDR 160 pins 80 LVDS pairs 80 pins 40 MHz DDR 160 pins 40 MHz DDR 80 pins 40 MHz DDR

  6. Design resources • Based on Los Alamos design • Double wide PMC developed for Lockheed Martin Space systems • >60% of current design retained • Los Alamos Team available • Contract in progress • Team has started work • Division of labor • CERN provides schematic modifications • Los Alamos checks design, lays out and fabricates prototypes

  7. Risk Assessment • Based on working design • Basic layout retained • Power supplies, decoupling layout • Plane structure • New elements • Many more high speed serial links • 32 instead of 8 • Congestion and signal integrity will be an issue • Optical interfaces • Used elsewhere in CMS • New FPGA package • FF1517 requires some modifications to decoupling cap layout • Risk defined by link density rather than speed • Serial links run at 1.6GBps • One half rated performance • Existing design tested to 2.5 GBps • Algorithm tests in current board define FPGA logic requirement • 30% headroom (2M gates/chip) at this point with no logic sharing

  8. Current Status • Schematics had been released • Algorithm testing identified logic capacity problem • Larger part required (V2P50 -> V2P70) • Package change required • Schematics need to be revised • Los Alamos aware of change • New symbols being built • One week of design time to recover • Both at CERN and Los Alamos • Los Alamos working without a contract • Eager to contribute

  9. Manpower and Schedule • One person at CERN • 3 months design (1/4 – ½ time) • Two at Los Alamos • 3 months layout (full time) • 1 month engineering (1/3 time) • 3 months to prototype order (ARO) • 4 months to first hardware delivery

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