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The von Neumann Model – Chapter 4

The von Neumann Model – Chapter 4. COMP 2620. The LC-3 as a von Neumann Machine. Memory. Memory contains the storage elements along with the MAR for addressing the memory elements The MDR holds the contents of a memory location to/from storage MAR is 16 bits, so the address space is 2 16

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The von Neumann Model – Chapter 4

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  1. The von Neumann Model – Chapter 4 COMP 2620 Dr. James Money COMP 2620

  2. The LC-3 as a von Neumann Machine

  3. Memory • Memory contains the storage elements along with the MAR for addressing the memory elements • The MDR holds the contents of a memory location to/from storage • MAR is 16 bits, so the address space is 216 • The MDR is 16 bits indicating each memory location is 16 bits

  4. Input/Output • There are two: • Keyboard • Monitor • For the keyboard, there are two registers: • KBDR – keyboard data register which has the ASCII code if the keys struck • KBSR – keyboard status register for status about the keys struck

  5. Input/Output • The monitor has also two registers: • DDR – ASCII code of the character to be displayed on the screen • DSR – the associated status information for the character to be printed on the screen • We will talk more about these in detail in Chapter 8

  6. Processing Unit • This consists of the • ALU – arithmetic and logic unit • Eight registers • R0,R1,…,R7 • Use to store temporary values • Also used as operands for operations

  7. Processing Unit • The ALU only has three operations: • Addition • Bitwise AND • Bitwise NOT • We will have to spend some time implementing the other functions to achieve full assembly language

  8. Control Unit • This contains the parts to control flow of the program executing • It contains the finite state machine, which directs all activity • Processing is carried out step-by-step and not clock cycle by clock cycle • There is the CLK input to the finite state machine which specifies how long each clock cycle lasts

  9. Control Unit • The Instruction Register (IR) is input to finite state machine and has the current instruction • This is input to the finite state machine since it determines what activities must be carried out • The Program Counter (PC) keeps track of the next instruction to be executed

  10. Instruction Processing • The most basic unit of processing is the instruction • There are two parts: • Opcode – what the instruction does • Operands – the parameters to the opcode, for example • Registers • Constants

  11. Instruction Processing • Each instruction is 16 bits, or one word on the LC-3 • The bits are numbered left to right from [15] to [0]. • Bits [15:12] contain the opcode • There are at most 24 = 16 opcodes • Bits [11:0] are operands

  12. Instruction Cycle • Each instruction is handled in a systematic way through a sequence of steps call the instruction cycle • Each step is called a phase • There are six phases to the cycle

  13. Instruction Cycle • The six phases of the instruction cycle are: • Fetch • Decode • Evaluate Address • Fetch Operands • Execute • Store Result

  14. Example: LC-3 ADD Instruction • LC-3 has 16-bit instructions. • Each instruction has a four-bit opcode, bits [15:12]. • LC-3 has eight registers (R0-R7) for temporary storage. • Sources and destination of ADD are registers. “Add the contents of R2 to the contents of R6,and store the result in R6.”

  15. Example: LC-3 LDR Instruction • Load instruction -- reads data from memory • Base + offset mode: • add offset to base register -- result is memory address • load from memory address into destination register “Add the value 6 to the contents of R3 to form amemory address. Load the contents of that memory location to R2.”

  16. Instruction with all six phases • Consider the Intel x86 instruction ADD [eax], edx • It loads data from the address located in eax and then adds it to the value in edx • The result is stored in the address located in eax

  17. Instruction with all six phases • This instruction requires all 6 phases • Fetch and Decode are required by all instructions • The address is eax is Evaluated and then it is Fetched • The add performs during Execute • The result is stored at the end

  18. Instruction types • So far, we’ve considered two instruction types: • Operate instruction – processes data, such as ADD • Data movement instruction – moves data from one place to another, such as LDR • There is a third type of instruction called the control instruction

  19. Instruction types • The control instruction changes the sequence of execution in the processing unit • Normally, the MAR is loaded from the PC at the beginning of processing • Thus, the control instruction must affect the PC value during the EXECUTE phase • We use this generate loops and branches

  20. Example: LC-3 JMP Instruction • Set the PC to the value contained in a register. This becomes the address of the next instruction to fetch. “Load the contents of R3 into the PC.”

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