HBD/TPC Electronics development

1. HBD/TPC Electronics development • For the TPC readout • How one would use the ALICE’s ALTRO chip • Using commercial version ADC + FPGA/ASIC • For HBT readout • How one distribute the preamp. with large pad • Can one drive signal out after preamp. ?? • If yes – can we use commercial version of electronics?? • Follow the development on TPC commercial solution • If no – we could follow what we did for TOF/EMC • Use QVC+AMU/TVC+AMU

2. Overall diagram for ALTRO chip

3. Backend of the ALTRO chip ALTRO’s event buffer could be divided to 8 * 512 word blocks or 4 * 1024 words blocks 15 write clocks Time signal L2 trigger (keep the buffer) L1 trigger (write to buffer) Read or drop L2 events L1 (W) L2 (keep) L1 (W) L1 (W) L2 (keep) L1 (W) L1 (W) L2 (keep) L1 (W) L1 (W) L1 (W) L1 (W) Problem for PHENIX: a) no overlapping events buffers (space between L1 triggers could be as short as 4 beam clocks) b) L1 trigger delay is too short, i.e. 15*25ns= 375ns.

4. If we would like to use ALTRO chip in PHENIX’s TPC… • We need to generate a fake L1 trigger every 512*25ns = 12.8 ms. ( used as L1 delay buffer) • Our L1 trigger will become ALTRO chip’s L2 trigger. • We read the L1 data buffers to a FPGA/ASIC. We will parse our data blocks from ALTRO data buffers Two overlapping TPC data block ALTRO 512 words buffers TPC data block PHENIX L1 Two PHENIX L1

5. Commercial ADC solution • Analog device is putting out a 4 channel 8-bits ADC with serial data output (260mw/chip at 65 MHz) (if power scale with clock => 40 mw/per channel at 40 MHz) (small size .65cm * .65cm) • We should build a prototype electronics with commercial version of ADC with FPGA. • Address the space/power/readout issues with commercial parts • In the long run, the commercial solution will improve in both size/power