Computer Organization CS224

1. Computer OrganizationCS224 Fall 2012 Lesson 23

2. Building a Datapath • Datapath • Elements that process data and addressesin the CPU • Registers, ALUs, MUX’s, memories, … • We will build a MIPS datapath incrementally • Refining the overview design §4.3 Building a Datapath

3. Instruction Fetch (IF) RTL Common RTL operations Fetch instruction Mem[PC]; Fetch instruction from memory Update program counter Sequential PC <- PC + 4; Calculate next address

4. Datapath: Instruction Fetch Unit Address Instruction Memory 4 PC Clk Adder Instruction Word 32

5. Add RTL Add instruction add rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] <- R[rs] + R[rt]; Add operation PC <- PC + 4; Calculate next address 6 5 5 5 5 6 Bits OP=0 rs rd sa funct rt function code (=32) second sourceregister first sourceregister resultregister shift amount

6. Sub RTL Sub instruction sub rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] <- R[rs] - R[rt]; Sub operation PC <- PC + 4; Calculate next address Bits 6 5 5 5 5 6 OP=0 rs rd sa funct rt function code (=34) second sourceregister first sourceregister resultregister shift amount

7. Datapath: Reg-Reg Operations R[rd] <- R[rs] op R[rt]; ALU control and RegWr coming from Control Unit, based on decoded instruction Ra, Rb, and Rw from rs, rt, rd fields RegWr Rd Rs Rt ALU control 5 5 5 Instruction busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32

8. OR Immediate RTL OR Immediate instruction ori rt, rs, imm Mem[PC]; Fetch instruction from memory R[rt] <- R[rs] OR ZeroExt(imm); OR operation with Zero-Extend PC <- PC + 4; Calculate next address Bits 6 5 5 16 OP rs imm rt immediate secondregister (dest) first sourceregister

9. Datapath: Immediate Ops Rw set by MUX and ALU B set as busB or ZeroExt(imm) ALUsrc and RegDst set based on instruction Rt Rd RegDst Mux Rt(Don’t Care) Rs ALU control RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 MUX ZeroExt imm16 32 16 ALUSrc

10. Load RTL Load instruction lw rt, rs, imm Mem[PC]; Fetch instruction from memory Addr <- R[rs]+ SignExt(imm); Compute memory address R[rt] <- Mem[Addr]; Load data into register PC <- PC + 4; Calculate next address Bits 6 5 5 16 OP rs imm rt immediate secondregister (dest) first sourceregister

11. Datapath: Load Extender handles sign vs. zero extension of immediate MUX selects between ALU result and Memory output Rt Rd RegDst Mux Rs Rt (Don’t Care) ALUctr RegWr 5 5 5 MemtoReg busA Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk MUX MemWr 32 32 MUX WrEn Adr Data In Data Memory Extender 32 imm16 32 16 Clk ALUSrc ExtOp

12. Store RTL Store instruction sw rt, rs, imm Mem[PC]; Fetch instruction from memory Addr <- R[rs]+ SignExt(imm); Compute memory addr Mem[Addr] <- R[rt]; Load data into register PC <- PC + 4; Calculate next address Bits 6 5 5 16 OP rs imm rt immediate second sourceregister first sourceregister

13. Datapath: Store Register rt is passed on busB into memory Memory address calculated just as in lw case Rt Rd RegDst Mux Rs Rt ALUctr RegWr 5 5 5 MemWr MemtoReg busA Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk MUX 32 32 MUX Data In WrEn Adr 32 Extender Data Memory imm16 32 16 Clk ALUSrc ExtOp

14. Branch RTL Branch instruction beq rs, rt, imm Mem[PC]; Fetch instruction from memory Diff <- R[rs] – R[rt]; Calculate branch condition if (Diff eq 0) Test if equal PC <- PC + 4 + SignExt(imm)*4;Calculate PC Relative address else PC <- PC + 4; Calculate next address Bits 6 5 5 16 OP rs imm rt immediate second source first source

15. Datapath: Branch Next Address Logic Rt Rd Clk Branch PC RegDst Mux Rt Rs ALUctr imm16 RegWr 5 5 5 busA 16 Rw Ra Rb busW 32 32 32-bit Registers ALU 32 To Instruction Memory Zero busB Clk 32 MUX Extender 32 imm16 16 ALUSrc More Detail to Come ExtOp

16. The Next Address PC is byte-addressed in instruction memory Sequential PC[31:0] = PC[31:0] + 4 Branch operation PC[31:0] = PC[31:0] + 4 + SignExt(imm) × 4 Instruction Addresses PC is byte addressed, but instructions are 4 bytes long Therefore 2 LSBs of the 32 bit PC are always 0 No reason to have hardware keep the 2 LSBs Simplify hardware by using 30 bit PC Sequential PC[31:2] = PC[31:2] + 1 Branch operation PC[31:2] = PC[31:2] + 1 + SignExt(imm)

17. Datapath: Fast, Expensive Next-IF Logic PC incremented to next instruction normally On beq instruction then can add immediate × 4 to PC + 4 30 Addr[31:2] 30 Addr[1:0] PC “00” 30 Instruction Memory Adder 30 MUX “1” Adder 32 Clk 30 SignExt 30 imm16 16 Instruction[31:0] Instruction[15:0] Branch Zero

18. Datapath: Slow, Smaller Next-IF Logic Slow because cannot start address add until ALU zero But probably not the critical path (LOAD is usually) PC Clk 30 Addr[31:2] 30 “1” Addr[1:0] “00” Carry In Instruction Memory “0” Adder MUX 30 32 SignExt imm16 30 30 16 Instruction[15:0] Instruction[31:0] Branch Zero

19. Jump RTL Jump instruction j target Mem[PC]; Fetch instruction from memory PC[31:2] <- PC[31:28] || target[25:0]; Calculate next address Bits 6 26 OP target jump target address

20. Datapath: IFU with Jump MUX controls if PC is pseudodirect jump PC Clk 30 Addr[31:2] 30 PC[31:28] Addr[1:0] “00” 4 Instruction Memory Target 30 26 Instruction[25:0] MUX 30 32 Adder 30 MUX “1” Jump Instruction[31:0] Adder 30 imm16 SignExt 30 16 Instruction[15:0] Zero Branch

21. Putting it All Together Instruction[31:0] Branch Instruction Fetch Unit Jump Rt Rd [0:15] [21:25] [16:20] [11:15] Clk RegDst Mux Rt Rs Rd Imm16 Rs Rt ALUctr RegWr 5 5 5 MemtoReg busA Zero MemWr Rw Ra Rb busW 32 32 32-bit Registers ALU 32 busB 32 Clk MUX 32 32 MUX Data In WrEn Adr 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp

22. A Real MIPS Datapath