Computer Organization CS224

1. Computer OrganizationCS224 Fall 2012 Lesson 26

2. Summary of Control Signals coding from green card func Not Important 10 0000 10 0010 op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add sub ori lw sw beq j 1 1 0 0 x x x RegDst 0 0 1 1 1 0 x ALUSrc 0 0 0 1 x x x MemtoReg 1 1 1 1 0 0 0 RegWrite 0 0 0 0 1 0 0 MemWrite 0 0 0 0 0 1 0 Branch 0 0 0 0 0 0 1 Jump x x 0 1 1 x x ExtOp Sub Add Sub Or Add Add xxx ALUctr<1:0>

3. Multilevel Decoding 12-input control will be very large (212 = 4096) To keep decoder size smaller, decode some control lines in each stage Since only R-type instructions (with op = 000000) need function field bits, give these to ALU control ALUctr op 6 Main Control 2 ALUop func 6 N ALU ALU Control (Local) Control signals to datapath

4. Multilevel Decoding: Main Control Table op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq j RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop<1:0> “R-type” Or Add Add xx Sub (compare with Fig 4.22)

5. ALU Control • ALU used for • Load/Store: F = add • Branch: F = subtract • R-type: F depends on funct field §4.4 A Simple Implementation Scheme

6. ALU Control • Assume 2-bit ALUOp derived from opcode • Combinational logic derives ALU control

7. 0 4 35 or 43 rs rs rs rt rt rt rd address address shamt funct 31:26 31:26 31:26 25:21 25:21 25:21 20:16 20:16 20:16 15:11 10:6 15:0 15:0 5:0 The Main Control Unit • Control signals derived from instruction R-type Load/Store Branch opcode always read read, except for load write for R-type and load sign-extend and add

8. Datapath With Control

9. R-Type Instruction

10. Load Instruction

11. Branch-on-Equal Instruction

12. 2 address 31:26 25:0 Implementing Jumps • Jump uses word address • Update PC with concatenation of • Top 4 bits of old PC • 26-bit jump address • 00 • Need an extra control signal decoded from opcode Jump

13. Datapath With Jumps Added Figure 4.24

14. Putting It All Together ALUop ALU Control ALUctr 3 RegDst func op 3 Main Control Instr[5:0] 6 ALUSrc 6 : Instr[31:26] Instruction[31:0] Branch Instruction Fetch Unit Jump Rt Rd [0:15] [21:25] [16:20] [11:15] Clk RegDst Mux 1 0 Rt Rs Rd Imm16 Rs Rt ALUctr RegWr 5 5 5 MemtoReg busA Zero Rw Ra Rb MemWr busW 32 32 32-bit Registers ALU 32 0 busB 32 Clk 0 MUX 32 32 MUX WrEn Adr 1 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp

15. Single Cycle Processor Advantages Single cycle per instruction makes logic and clock simple All machines would have a CPI of 1 Disadvantages Inefficient utilization of memory and functional units since different instructions take different lengths of time Each functional unit is used only once per clock cycle e.g. ALU only computes values a small amount of the time Cycle time is the worst case path long cycle times! Load instruction PC CLK-to-Q + instruction memory access time + register file access time + ALU delay + data memory access time + register file setup time + clock skew All machines would have a CPI of 1, with cycle time set by the longest instruction!

16. Performance Issues • Longest delay determines clock period • Critical path: load instruction • Instruction memory  register file  ALU  data memory  register file • Not feasible to vary period for different instructions • Violates design principle • Making the common case fast • We will improve performance by pipelining

17. Summary Processor Input Control Memory Datapath Output • Single cycle datapath => CPI=1, CCT => long • 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • Control is the hard part • MIPS makes control easier • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates