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ELEC 7770 Advanced VLSI Design Spring 2016 Clock Skew Problem

Understand the concept of clock skew in VLSI design, its impact on timing constraints, and techniques to minimize skew.

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ELEC 7770 Advanced VLSI Design Spring 2016 Clock Skew Problem

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  1. ELEC 7770Advanced VLSI DesignSpring 2016Clock Skew Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr16/course.html ELEC 7770: Advanced VLSI Design (Agrawal)

  2. Single Clock FF A FF B Comb. Data_out Data_in CKA CKB CK CKA CKB Single-cycle path delay ELEC 7770: Advanced VLSI Design (Agrawal)

  3. Multiple Clocks FF A FF B Comb. Data_out Data_in CKA CKB CKA CKB Multi-cycle path delay ELEC 7770: Advanced VLSI Design (Agrawal)

  4. Clock Skew • Skew is the time delay of clock signal at a flip-flop with respect to some time reference. • For a given layout each flip-flop has a skew, measured with respect to a common reference. • Skews of flip-flops separated by combinational paths affect the short-path and long-path constraints. ELEC 7770: Advanced VLSI Design (Agrawal)

  5. Skews for Single-Cycle Paths Combinational Block Delay: FFi CKi FFj CKj δ(i,j) ≤ d(i,j) ≤ Δ(i,j) si sj si and sj are arrival times of clock edges w.r.t. a reference time ELEC 7770: Advanced VLSI Design (Agrawal)

  6. Delay Latch or D-Latch SR-latch D CK Q Q ELEC 7770: Advanced VLSI Design (Agrawal)

  7. Setup and Hold Times of Latch • Signals are synchronized with respect to clock (CK). • Operation is level-sensitive: • CK = 1 allows data (D) to pass through • CK = 0 holds the value of Q, ignores data (D) • Setup time is the interval before the clock transition during which data (D) should be stable (not change). This will avoid any possible race condition. • Hold time is the interval after the clock transition during which data should not change. This will avoid data from latching incorrectly. ELEC 7770: Advanced VLSI Design (Agrawal)

  8. Why Do We Need Setup? SR-latch D CK=1 Latch open Q Q Legal inputs are 10 or 01 when Latch closes ELEC 7770: Advanced VLSI Design (Agrawal)

  9. Latch Inputs tp 1 0 D time Ts Th Tc.Q 1 0 CK time Tr Tc.Q : Clock to Q delay ELEC 7770: Advanced VLSI Design (Agrawal)

  10. Master-Slave D-Flip-Flop Master latch Slave latch D CK Q Q ELEC 7770: Advanced VLSI Design (Agrawal)

  11. Master-Slave D-Flip-Flop • Uses two level-sensitive clocked D-latches. • Transfers data (D) with one clock period delay. • Operation is edge-triggered: • Negative edge-triggered, CK = 1→0, Q = D (previous slide) • Positive edge-triggered, CK = 0→1, Q = D ELEC 7770: Advanced VLSI Design (Agrawal)

  12. Negative-Edge Triggered D-Flip-Flop Clock period, Tck Slave open Master closed Master open Slave closed CK D Triggering clock edge Hold time, Th Setup time, Ts Clock-to-Q delay, Tc.Q Data stable Data can change Data can change Time ELEC 7770: Advanced VLSI Design (Agrawal)

  13. Skews for Single-Cycle Paths Combinational Block Delay: FFi CKi FFj CKj δ(i,j) ≤ d(i,j) ≤ Δ(i,j) si sj skews, si and sj are delays from a common clock generator ELEC 7770: Advanced VLSI Design (Agrawal)

  14. Short-Path Constraint (Double-Clocking) Tck CKi si intended Not intended CKj Thj sj δ(i,j) Condition to avoid double clocking: si + Tc.Q + δ(i,j) ≥ sj + Thj ELEC 7770: Advanced VLSI Design (Agrawal)

  15. Long-Path Constraint (Zero-Clocking) Tck CKi si Not intended intended CKj sj Tsj Tc.Q+ Δ(i,j) Condition to avoid zero clocking: si + Tc.Q + Δ(i,j) ≤ sj + Tck – Tsj ELEC 7770: Advanced VLSI Design (Agrawal)

  16. Maximum Clock Frequency Linear program: Objective function, Minimize Tck Subject to constraints, for all flip-flop pairs (i,j), (1) si + Tc.Q + δ(i,j) ≥ sj + Thj short path (2) si + Tc.Q + Δ(i,j) ≤ sj + Tck – Tsj long path ELEC 7770: Advanced VLSI Design (Agrawal)

  17. Effects of Constraints • Short path: • Independent of clock • Minimum path delay: δ(i,j) ≥ sj – si – Tc.Q + Thj • Long path: • Minimum clock priod: Tck ≥ si – sj + Tc.Q + Δ(i,j) + Tsj • Example: Shift register, assume δ(i,j) ≈ Δ(i,j) ≈ 0 • si – sj ≥ Thj – Tc.Q > 0, si > sj for correct operation • Tck ≥ si – sj + Tc.Q + Tsj, sj > si for maximum speed • Clock routed opposite to data ELEC 7770: Advanced VLSI Design (Agrawal)

  18. Shift Register Example Delay ≈ 0 Delay ≈ 0 FFi FFj FFk Delay = si sj sk CK Rk Rj Ri Ci Cj Ck si + Tc.Q – sj ≥ Thj for correct operation Tck ≥ si – sj + Tc.Q + Tsj for correct operation Tck + si + Tc.Q – sj ≥ si – sj + Tc.Q + Tsj + Thj adding two inequalities Maximum clock speed: Tck = Tsj + Thj ELEC 7770: Advanced VLSI Design (Agrawal)

  19. Finding Clock Skews sk FFi FFj FFk si CK Ri Rj Rk Ci Cj Ck sj Use Elmore delay formula to calculate si, sj, sk. ELEC 7770: Advanced VLSI Design (Agrawal)

  20. Interconnect Delay: Elmore Delay Model • W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948. i Rj Ri Rk j k CK Ci Shared resistance: Rii = Ri Rij = Rji = Ri Rik = Rki = Ri Rjj = Ri + Rj Rjk = Rkj = Ri + Rj Rkk = Ri + Rj + Rk Cj Ck ELEC 7770: Advanced VLSI Design (Agrawal)

  21. Elmore Delay Calculation Delay at nodes, sk = 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk ) = 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck] sj = 0.69 [Ri Ci + (Ri + Rj) (Cj + Ck)] si = 0.69 [Ri (Ci + Cj + Ck)] ELEC 7770: Advanced VLSI Design (Agrawal)

  22. Example i 1Ω 1Ω 1Ω j k CK 1pF 1pF 1pF si = 0.69 × 3 ps sj = 0.69 × 5 ps sk = 0.69 × 6 ps ELEC 7770: Advanced VLSI Design (Agrawal)

  23. Finding δ(I,j) and Δ(I,j) Minimum delay Maximum delay , - , - A 1 , - 9, 10 H 3 j , - 0, 0 3, 3 B 3 4, 4 i E 1 G 2 6, 7 , - , - C 1 , - 6, 8 J 1 F 1 k , - , - 5, 5 D 2 , - ELEC 7770: Advanced VLSI Design (Agrawal)

  24. Maximum Clock Frequency for Tolerance ±q/2 in Skew Linear program: Minimize Tck Subject to: For all flip-flop pairs (i,j), si + δ(i,j) ≥ sj + Thj + q si + Δ(i,j) ≤ sj + Tck – Tsj – q Where q is a constant si are variables, simin ≤ si Tck is a variable ELEC 7770: Advanced VLSI Design (Agrawal)

  25. Maximum Tolerance for Given Clock Frequency Linear program: Maximize q Subject to: For all flip-flop pairs (i,j), si + Tc.Qi + δ(i,j) ≥ sj + Thj + q si + Tc.Qi+ Δ(i,j) ≤ sj + Tck – Tsj – q Where Tck, Tc.Qi, Thj and Tsj are constants si are variables, simin ≤ si q is a variable ELEC 7770: Advanced VLSI Design (Agrawal)

  26. Tradeoffs No solution because of zero slack. Increasing skew tolerance q Increasing clock period Tck ELEC 7770: Advanced VLSI Design (Agrawal)

  27. Clock Skew Problem • N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999. • J. P. Fishburn, “Clock Skew Optimization,” IEEE Trans. Computers, vol. 39, no. 7, pp. 945-951, July 1990. ELEC 7770: Advanced VLSI Design (Agrawal)

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