Overview of PTIDES Project

1. Overview of PTIDES Project JiaZou Slobodan Matic Edward Lee Thomas HuiningFeng Patricia Derler University of California, Berkeley

2. Reliable and Evolvable NetworkedTime-Sensitive Systems, Integrated with Physical Processes • Cyber Physical Systems:

3. CPS Requirements – Printing Press • Application aspects • local (control) • distributed (coordination) • global (modes) • Open standards (Ethernet) • Synchronous, Time-Triggered • IEEE 1588 time-sync protocol • High-speed, high precision • Speed: 1 inch/ms • Precision: 0.01 inch • -> Time accuracy: 10us • Bosch-Rexroth Orchestrated networked resources built with sound design principles on suitable abstractions DETERMINISM TIMED SEMANTICS

4. PTIDES: Analysis Schedulability Analysis Causality Analysis Program Analysis Ptides Model Code Code Generator PtidyOS HW Platform Software Component Library Mixed Simulator HW in the Loop Simulator Plant Model Network Model

5. PTIDES Model • Programming Temporally Integrated Distributed Embedded Systems • Based on Discrete-Event model of computation • Event processing is in time-stamp order • Deterministic under simple causality conditions • fixed-point semantics • super-dense time

6. Causality Interface • Software components are actor-oriented • All actors are reactive • Consume input event(s) and produce output event(s) • Sensors react to the physical environment • Interface represented by δ • δ is the minimum model time delay from the input to the output • Compositionality properties: Min-plus algebra Actor A τ τ’ δ τ’ ≥ τ + δ δ δ

7. Model vs. Physical Time • At sensors and actuators • Relate model time (τ) to physical time (t) t ≥ τ t ≤ τ τ1 do i4 model time τ1 τ4 0 physical time t1 t4 0

8. Single Processor PTIDES Example • Bounded sensor latency (d0) t ≥ τ, t ≤τ + do t ≤ τ τ1 do i4 τ2 model time τ2 0 physical time t2 0 e2 ati2

9. Single Processor PTIDES Example t ≥ τ , t ≤τ + do t ≤ τ τ1 do i4 τ2 model time τ2 0 physical time t2 τ2+d0 0 e2 safe to process if t > τ2 + do

10. Single Processor PTIDES Example t ≤τ + do t ≤ τ τ1 do i4 τ2 model time τ1 0 physical time t2 τ1+ d0 0 e2 safe to process if t > τ2 + do

11. Distributed PTIDES Example • Local event processing decisions: • Bounded communication latency (d0) • Distributed platforms time-synchronized with bounded error (e) d 1 τ1 τ3 Sensor d01 τ4 τ2 τcannot be rendered unsafe by events from outside of the platform at: t > τ+ do2 + e - d2 Network Interface do2 o3 Merge τ Actuator d 2

12. Distributed PTIDES Example • Local event processing decisions: • Bounded communication latency (d0) • Distributed platforms time-synchronized with bounded error (e) τ3 Sensor d01 τ4 τ1 may result in future event of timestamp τ1’≥ τ1 + d1 d 1 Network Interface τ1 do2 o3 Merge τ Actuator d 2

13. General Execution Strategy • An event e is safe to process if no other event e’ may render e unsafe • out of the platform -> clock test • within the same platform as e -> model delay test τ3 Sensor d01 τ4 For all events within the platform: τi+ di ≥ τ d 1 Network Interface τ1 do2 o3 Merge τ Actuator d 2 τcannot be rendered unsafe by events from outside of the platform at: t > τ+ do2 + e - d2

14. What Did We Gain? First Point: Ensures deterministic data outputs Merge e1 = (v1, τ1) δ e1, e2, … safe to process analysis for e safe to process analysis for e e2 = (v2, τ2) Second Point: Ensures deterministic timing delay from Sensor to Actuator t ≤τ + do t ≤ τ τ1 do i4 τ2

15. What’s More… Third Point: Decoupling of design from hardware platform Schedulability analysis

16. PTIDES: Analysis Schedulability Analysis Causality Analysis Program Analysis Ptides Model Code Code Generator PtidyOS HW Platform Software Component Library Mixed Simulator HW in the Loop Simulator Plant Model Network Model

17. Schedulability Analysis • Requires WCET of software components + event models • Three cases: • Zero event processing time assumption (feasibility test) • if P fails, P will not satisfy constraints on any hardware • No resource sharing assumption (an event is processed as soon it is safe) • if P fails, P may still satisfy constraints on other hardware • Resource sharing (a safe event is processed according to a scheduling algorithm) • if P fails, P does not satisfy this implementation (and algorithm)

18. PTIDES Scheduler Implementations • Two layer execution engine • Event coordination (safe-to-process) • Event scheduling (prioritize safe events) • Earliest Deadline First foundation • EDF is optimal with respect to feasibility • Deadline based on path from input port to actuator Actuator Actor A e1 = (v1, τ1) δ Deadline(e1) = τ1+ δ

19. PTIDES: Analysis Schedulability Analysis Causality Analysis Program Analysis Ptides Model Code Code Generator PtidyOS HW Platform Software Component Library Mixed Simulator HW in the Loop Simulator Plant Model Network Model

20. PtidyOS • Lightweight real-time operating system (RTOS) • Software components (actors) are “glued together” by a code generator into an executable • Scheduler combine EDF with PTIDES • Process events in deadline order • Interrupts • All execution are done within ISR • Reentrant interrupts • Experimenting with Luminary board with IEEE1588 support

21. PTIDES Program Design Workflow PtidyOS HW Platform