Liquid Processor Platform

1. Liquid Processor Platform Team members: Phillip Jones (team lead) Shobana Padmanabhan John Maschmeyer Daniel Rymarz Visit : http://www.arl.wustl.edu/arl/projects/fpx/cse535/projects/

2. End Result LEON Processor SDRC SDRAM UART AHB Adapter Serial port APB Adapter Virtual Device Driver Key LED Driver LEDs Project tasks Control IP Packets gigE Future tasks Control S/w • The end goal of this project is to develop a soft core embedded processor system that can be programmed over a network connection.

3. Motivation • Soft-core embedded Processor: • Very flexible processor that would be useful for quickly prototyping systems with different parameters (e.g. pipe-line depth, cache size, hardware-accelerated instructions, etc.) to perform performance evaluations • Programmable / Configurable over a Network: • A must if the system is to be used via the Internet

4. Design Approach • Start with Leon Processor base • Supplies many of the components that will be needed in the end system. • UARTS • Processor • General I/O Drivers • System/Processor Bus (AMBA) • Develop and Integrate in new features • AMBA to SDRAM Controller Adapter • Control SW • Control Packet routing • Validation Environment

5. Interfaces and Components LEON Processor SDRC SDRAM UART AHB Adapter Serial port APB Adapter Virtual Device Driver Key LED Driver LEDs Project tasks Control IP Packets gigE Future tasks Control S/w

6. Tasks • Validation/Cofig/Build Environment • Emulation of external stimuli • GigE, SDRAM • Configuration of Liquid Architecture • Cahce size, MMU • Integration of Leon core code, scripts with project code • Sparc Assembly programming &/ Cross-compiler code generation • Programming simple test programs for the LEON processor • SDRAM Interface • Need detailed knowledge in order to create AMBA-SDRAM controller interface

7. Tasks (cont.) • Control SW • Automate tasks (e.g. Load Program, read/write SDRAM location “x”, Reset Processor …) • Definitions of control packets • Control Packet Process • Directing the appropriate Control packets to SDRAM, Debug unit

8. Validation/Config/Build Environment (phjones) • Integration of project code into existing Leon core code/configuration scripts • Leon core has an existing tk/tcl configuration environment (should be leveraged if possible) • Validation environment • Use Leon core validation environment as a base • Integrate project specific validation code • Build project for FPX • Modify exiting Leon core scripts to build with project specific code.

9. Sparc Assembly programming • Sparc Assembly programming &/ Cross-compiler code generation • Programming simple test programs for the LEON processor

10. Interface to SDRAM Controller (jrm) • SDRAM must be accessed by Control Packet Processor and Processor Core • FPX SDRAM Controller • Provides arbitrated access to SDRAM for up to three devices • Support for burst transfers up to 256 words

11. Interface to SDRAM Controller (jrm) • Connecting to CPP • Simple State Machine to Perform Handshaking • Connecting to LEON Core • Replace existing SDRAM Controller • Build adapter to bridge FPX SDRAM Controller to LEON memory controller • Other Key Issues • Support for additional memory types • Changing the LEON address space

12. Control SW (sp) • Control SW • Automate tasks (e.g. Load Program, read/write SDRAM location “x”, Reset Processor …) • Definitions of control packets

13. Control SW (sp) • Control packet formats

14. Control packet for write

15. Control packet for start, halt CPU

16. Control packet for read