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ERC - Elementary Readout Cell

This board features an Altera Cyclone III FPGA, LV regulation circuits, on-board sensors, USB and optical links, external connectors, and more. It is a versatile development tool for testing and prototyping.

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ERC - Elementary Readout Cell

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  1. ERC - Elementary Readout Cell Miguel Ferreira 18th April 2012 Miguel@Lip.pt

  2. ERC Prototype Board • MAROC3 chip (PQFP240 package) • Altera Cyclone III (EP3C80F780C7N) • LV regulation circuits (AVDD, VDD, VCIO, 3V3, 1V2,…) • Bias supply regulation (DAC 14 Bits I2C) • Bias supply monitoring (ADC I2C) • 7 on-board sensors (TMP100 I2C) • Internal CLK LVDS (125/60/40/80 MHZ) • Humidity sensor (I2C) • USB link (FPGA DATA OUT) • 2 SFP Optical Link (FPGA DATA OUT) • External CLOCK connector • External SYNC connector • External NIM TRIGGER connector • JTAG Connector • External ASIC output monitoring connectors (charge, SUM08) • Internal ASIC test pulse (common to 64 channels)

  3. ERC Prototype Board Bias Test pulse Charge Out LV PWR USB Humidity TEMP RS232 64 ch SiPM Matrix MAROC3 FPGA Serdes Opt.transceiver 64 switch Serdes Opt.transceiver SYNC IN CLK PROM Cold plate MPPC Bias Control DAC SYNCOUT JTAG SUM08 SUM08 SUM08 Bias Control ADC CLK EXT

  4. SiPM Analog Input with 50 ohm impedance control

  5. HV Regulation & Distribution 5 volts range with a 0.3mV LSB SiPM Array

  6. Cyclone III FPGA HSTL HSTL LVDS LVDS LVDS LVDS LVCMOS LVCMOS

  7. Optical Link up to 3.125Gbps Transceiver from National Semicondutor

  8. ERC Schematics Layout Setting the Rules on Schematics Level for a better design control

  9. PCB Layer Stack Manager • Setting the Digital and Analog Layers • Setting the Digital and Analog Power Plane

  10. Signal Integrity Analysis Bad termination Increases signal Reflections which incraesesthe overrall noise impact.

  11. ERC Prototype Board Status and Plans

  12. ERC Prototype Board Status and Plans • ThreePCB´s In production • Assembly the Board over (1700 Components)

  13. Thank you Questions?

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