1 / 15

What’s New in Xilinx Ready-to-use solutions

What’s New in Xilinx Ready-to-use solutions. Key New Features of the Foundation Series 1.5/1.5i Release. New device support Integrated design environment with advanced design flow automation control Full verilog support “Point” tool productivity enhancements Design tools Synthesis

jlauterbach
Download Presentation

What’s New in Xilinx Ready-to-use solutions

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. What’s New in Xilinx Ready-to-use solutions

  2. Key New Features of the Foundation Series 1.5/1.5i Release • New device support • Integrated design environment with advanced design flow automation control • Full verilog support • “Point” tool productivity enhancements • Design tools • Synthesis • Implementation tools • Web-enabled Design Features

  3. Foundation Series 1.5New Device Support • XC9500 XL - true ISP, 3.3V cplds • Spartan XL - no compromise architecture at 3.3V • Virtex - system level programmable logic • Continued device support for: • Xc3000x, xc3100x, XC4KX, XC5200, XC9500, spartan

  4. Foundation Series 1.5Integrated Design Environment • Synopsys FPGA Express 2.1 directly embedded within foundation PCM • Xilinx implementation tools with A.K.A. Speed Technology embedded within PCM • Aldec’s Active-VHDL direct push button interface (purchased as an option from Aldec)

  5. Foundation Series 1.5Full Verilog Support • State Editor Now Generates Verilog HDL • Full HDL Editor Support • Color Coding • Language Assistant Verilog Templates • Verilog HDL Syntax Checking • Schematic Editor • Supports Verilog Modules (Macros) • Verilog Source Code Debugging via MTI* * Evaluation copies of ModelSim are included with all Foundation Series HDL packages. Licensed, Sold, and Supported separately by Model Technology Inc.

  6. Foundation Series 1.5Point Tool Enhancements • Synthesis (FPGA Express) • Implementation Tools (A.K.A. Speed Technology) • Schematic Editor • HDL Editor • Gate Level Simulator

  7. Point Tool EnhancementsExpress Synthesis • Embedded with foundation series PCM • Virtex specific optimization • Addition of important VHDL ‘93 constructs • Endkeyword - component keyword • Is keyword - labels on assignments • T’image(x) - block in generate • Alias keyword - array slices with others • Addition of other HDL constructs • Rising_edge/falling_edge • ‘Else • Hex, octalandbinaryfor std_logic_vectors

  8. Point Tool EnhancementsExpress Synthesis • State machine synthesis options • FSM Encoding Style • One Hot • Binary • FSM Extraction Method • Safest (all possible states) • Smallest (defined states only)

  9. Point Tool EnhancementsImplementation Tools • Embedded within foundation series PCM • A.K.A. Speed technology • Device floorplanner • Xilinx constraints editor • New timespecs • Temperature pro-rating • Min-delays • K-paths timing analysis algorithm

  10. Point Tool EnhancementsSchematic Editor • Re-implemented bus behavior • Complex buses • Bus editing now similar to wire editing • Enhanced wire behavior • Selection, deletion • Autowiring / rubberbanding • Local menus (e.g., right-click > hierarchy push, copy/paste, symbol properties, etc.) • “SC symbols” dialog box enhanced - project components separated from unified library comps

  11. Point Tool EnhancementsSchematic Editor (continued) • “Replace symbol” option now has a drop-down selector from which to pick new symbol • Symbol attributes can now be moved directly (no need to bring up properties dialog) • Multi-level undo (5 levels) • Copy/paste enhancement: objects to be pasted are visible as copy buffer is moved around on the schematic • Enhanced CORE generator 1.5 interface (i.E., Symbol generation)

  12. Point Tool EnhancementsHDL Editor • New “insert file” item in edit menu • Provides easy method for insertion of logiblox and CORE generator created instantiation templates • Verilog syntax checking, color-coding, language templates, schematic flow macro synthesis • VHDL language assistant templates updated to be express compliant

  13. Point Tool EnhancementsGate-Level Simulator • Virtex LUT support • Some limitations at first release; may be addressed in performance pack • Typical user will want to use behavioral simulator anyway • Memory allocation tuning to support larger netlists • Signal selection dialog “search” feature enhanced

  14. Point Tool EnhancementsGate-Level Simulator (continued) • New simulation script wizard • Invoke at script editor start-up or • Invoke from script editor’s tools menu • “Enable global netlist analysis” feature • May speed up simulation if disabled • Project-specific (not always needed)

  15. Foundation Series 1.5 Web-enabled Design Features • Integrated into Project Manager • Instant Access to http://support.xilinx.com • Netscape and MS Explorer compatible News Bulletins Searchable Knowledge Base(includes agent reports) Designer Tools & Services

More Related