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Serial Power Distribution for the ATLAS SCT Upgrade

Serial Power Distribution for the ATLAS SCT Upgrade. John Matheson Rutherford Appleton Laboratory On behalf of the SP Community. Thanks to Richard Holt (RAL), Dave Lynn (BNL) and Peter Phillips (RAL). Outline. the SCT upgrade powering issues for the SCT upgrade

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Serial Power Distribution for the ATLAS SCT Upgrade

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  1. Serial Power Distributionfor the ATLAS SCT Upgrade John Matheson Rutherford Appleton Laboratory On behalf of the SP Community Thanks to Richard Holt (RAL), Dave Lynn (BNL) and Peter Phillips (RAL)

  2. Outline the SCT upgrade powering issues for the SCT upgrade the serial powered detector stave concept SP implementations in more detail a practical SP stave architecture SP stave test results (ABCD FEICs) test results with ABCnext FEICs test results with SPI (serial power interface ASIC) work in progress and in future summary and conclusions

  3. The present SCT present ATLAS SCT: 4088 detector modules 3.2M channels upgrade SCT: need 34 M channels to cope with increased luminosity current SCT module design 768 chan/side

  4. Powering the present SCT • 4088 Detector Modules • Independent Powering • 4088 cable chains • 22 PS racks • 4 crates / rack • (up to) 48 LV and 48 HV channels / crate • Overall efficiency ~40% • Cable R => voltage drops

  5. layout of the Upgraded SCT detector staves arranged into barrels detector petals arranged into discs

  6. The SP stave concept staves carry 12 detectors, 24 readout modules each module carries 20 ABCn ROICs a serial powering chain is a natural option each module must carry a shunt regulator to keep supply V constant powering by DC-DC converters is a competing option, or a complementary option 6

  7. Shunt Regulator Architectures • Hybrid with Shunt “W” • Use each ABCN’s integrated shunt regulator • Use each ABCN’s integrated shunt transistor(s) • Hybrid with Shunt “M” • Use one external shunt regulator • Use each ABCN’s integrated shunt transistor(s) • Two (redundant) shunt transistors, 140mA each • Hybrid with SPi (or similar) • Use one external shunt regulator • Use one external power transistor All now available in silicon: final choice to be based upon test results.

  8. Efficiency = power consumed by ABCN H power delivered to hybrid Highest Efficiency:SP with on-chip DC-DC conversion using switched capacitors Lowest Noise:SP with on-chip Linear Regulatorsfor both Analogue and Digital Eff = 55%Eff = 50% Eff = 77%Eff = 75% Efficiency = H H D D power consumed by ABCN D power delivered by power supply SP Options in more detail Some assumptions: Cable resistance 2 ohms for each line pair, SR = 85%, low current DC-DC = 90%, high current DC-DC = 85% Bus cable traces 7.5mm wide, 18 micron Cu chip power is that projected for 130nm ABCn ABCN demand power is dependent on task. This will normally mean a shunt regulator will dissipate some power to maintain voltage under all conditions.

  9. Comparison – DCDC, IP Off-chip DC-DC conversion from 10V to 2.4V and 1.8V(assume 85% efficiency)“On-chip” DC-DC conversion using switched capacitors(assume 90% efficiency) Eff = 76%Eff = 40% H D Eff = 100%Eff = 1% Independent Power H D With ABCN in 130 nm technology, we shall study the options to obtain the best trade-off between efficiency and performance…

  10. SP Stave Architecture 24 hybrids in series, each at different potential wrt GND CLK & COM AC coupled at hybrid DATA AC coupled at end of stave Common GND at end of stave (DC-DC powered stave would look similar, apart from the absence of AC coupled IO)

  11. Protection of SP against faults Whilst demonstration staves have generally been reliable: What happens if a module fails open circuit? What happens if a module becomes a noise generator? How to turn modules on/off? We could provide a system to “short out” each module under control of DCS Voltage across shorted module should be small (<100mV) Area of components and number of control lines must be small Automatic over current and over voltage protection is desirable Protection circuit must draw no (minimal) power when module active Ability to put modules into “stand by” (low power state)

  12. AC coupled data transmission - prototype bus tape Whether we use SP or not, need to minimize number of signal traces in stave => multi-drop Test stave at Oxford Cu/kapton + Al screen layer Send “TTC” data from FPGA  24 dummy hybrids with receiver/drivers Loopback data on dummy hybrids FPGA  BERT. Measure BERT for balanced and unbalanced data, parallel and serial powering Balanced code works fine. M-LVDS + Serial powering + balanced code ok, ie no errors found in 3 locations tested (3 ,12 and 24).

  13. Serial Powering and HV Standard HV powering: one HV per module Alternative HV powering: one HV supply per M modules • Serial Powering is compatible with the use of a single HV supply for several modules • Each sensor is dynamically connected to current source ground through output impedances of the chain of shunt regulators • Low shunt output impedance is crucial to achieve good ‘grounding’ and reduce noise

  14. System tests of SP staves – Stave 07 Thick Film Hybrid for 6 ABCD chips with integrated Serial Powering circuitry: requires ~0.75A at 4V • We have verified that: • Noise is not an issue • AC coupled (M)LVDS works • SP uses little extra real estate • Can use single HV line / strip stave • stave working well ! Stave07: 30 module stave with ABCD 30 * 4V = 120V (ABCD, 800nm) Future: 24 * ~1V = 24V for 130nm ABCN

  15. ABCD Noise Slope SCT Barrel Module independent powering serial powering Bare Chip independent powering SP does not increase noise !

  16. First tests of integrated shunts in ABCN:RAL single chip PCB and Liverpool Hybrid this is the most recent generation of FEIC: ABCn in 250nm CMOS next step: ABCn in 130nm CMOS

  17. Single Chip using shunt “M” IP result 380 ENC: SAME!

  18. ABCN hybrid using shunt “W” PRELIMINARY ENC 450 e- RMS

  19. Shunt regulator schemes Data communication Power management Monitoring/alarms Designed by Marcel Trimpl (FNL) Mitch Newcomer (U Penn) What is SPi? SPi (Serial Power Interface): • flip chip, bump bonded • 144 pads (68 I/O, 76 power) • Sub-set used for each application 2.7 mm 5.5 mm

  20. Example tests on SPI Communication works well Programmable shunt regulator OK Power line Control clock Data in Data out Programmable linear regulators (mostly) work reliably

  21. SPi with a hybrid SPi = “Serial Powering interface”… • Shunt regulator schemes ABCN with SPi internal shunt regulator ABCN with SPi controlling distributed shunt transistors • Data communication Data has passed through SPi • Power management Shunt current monitoring Shunt regulator voltage setting Linear regulators voltage setting Alarm = tested and working Documentation is available to users

  22. The Stavelet ATLAS community stavelets are planned Data & hybrid communication Power & power control communication (SPi) The power plug-in concept Distributed SPi DC-DC Allows comparison of different power configurations Different bus cable designs Different grounding and shielding concepts Stavelets early 2010, realistic stave late 2010 ? Stavelets allow option choices

  23. SP Summary and Next Steps • Staves have been built with commercial SP components • Shunt circuitry has now been integrated into FE chips • Protection can be part of SP architecture • AC coupling works well with balanced codes • HV distribution is understood • A custom current source is available • First ABCN demonstrator stavelet planned for this year • Integrated shunts + protection • Possibility of testing different SP, G+S options • Will be used to choose options for Stave09 • SP is an attractive option for sLHC power distribution

  24. Spare slides

  25. Power Requirements with Modern Process Technologies Power per 128 channel chip per channel In ATLAS SCT ABCD (0.8m, biCMOS) Digital: Analogue: 4.0 volts 3.5 volts 35 mA per chip (actual) 74 mA per chip (actual) => 4.0 x 35 + 3.5 x 74 = 399 mW 3.1 mW Present Prototype ABCN25 (0.25m CMOS) Digital: Analogue: 2.5 volts 2.2 volts 95 mA per chip (preliminary) 27 mA per chip (preliminary) => 2.5 x 95 + 2.2 x 27 = 300 mW 2.3 mW Proposed ABCN13 (0.13m CMOS) Digital: Analogue: 0.9 volts 1.2 volts 51 mA per chip (estimate) 16 mA per chip (estimate) => 0.9 x 51 + 1.2 x 16 = 65 mW 0.5 mW ** ** • ABCN25: Vdig > Vana Idig >> Iana • If we generate Vana from Vdig using LR: • 27mA * 0.3V = 8.1mW per chip • 3% of chip power • ABCN13: Vana > Vdig Idig >> Iana • If we generate Vdig from Vana using LR: • 95mA * 0.3V = 28.5mW per chip • 44% of chip power • Can we do better than this? Of course… ** Power Estimates for an ABCN in 130nm Technology, Mitch Newcomer, Atlas Tracking Upgrade workshop, NIKHEF, November 2008 http://indico.cern.ch/getFile.py/access?contribId=16&sessionId=8&resId=0&materialId=slides&confId=32084

  26. Efficiency - definitions Definition – Hybrid (excludes stave interconnects & supply cables) Efficiency = Efficiency H power consumed by ABCN H power delivered to hybrid Definition – Detector (includes all supply cables) Efficiency = Efficiency D power consumed by ABCN D power delivered by power supply Some assumptions: Cable resistance 2 ohms for each line pair, SR = 85%, low current DC-DC = 90%, high current DC-DC = 85% ABCN demand power is dependant on task. This will normally mean a shunt regulator will dissipate some power to maintain voltage under all conditions.

  27. Detector power efficiency Independent powering (100% hybrid efficiency) 1 stave = 24 hybrids = 480 ABC-N (0.13 m) Power (voltage) 2633 Watts 3 Watts 2668 Watts 0 Watts 32 Watts Efficiency = 1% D Independent supplies (line pairs) for digital and analogue power. Same amount of copper => Cables are 96 ohms total for each line pair. Each line pair carries 20 x 51mA (digital) and 20 x 16mA (analogue). Numbers rounded

  28. Detector power efficiency Serial powering 3.6V, 3:1 & 4:1 DC-DC using switched capacitors 1 stave = 24 hybrids = 480 ABC-N (0.13 m) Power (constant current) 0.5 Watts 0.5 Watts 43 Watts 9.6 Watts (77% efficiency ) H 32 Watts Efficiency = 75% D Cables assumed to be 2 ohms total for each power line pair Regulator power = (1/eff - 1) x ABC power H Stave supply current = (32 + 9.6 + 0.5)watts / (3.6volts x 24) = 0.49amps Numbers rounded

  29. Richard Holt – Rutherford Appleton Laboratory Combined SP & DC-DC powering options November 2008 Detector power efficiency Two-stage DC-DC powering (78% hybrid efficiency) 1 stave = 24 hybrids = 480 ABC-N (0.13 m) Power (voltage) 34 Watts 1.3 Watts 9 Watts 76 Watts (78% efficiency ) H 32 Watts Efficiency = 42% D Cables assumed to be 2 ohms total for each power line pair Regulator power = (1/eff - 1) x ABC power Stave supply current = (32 + 9)watts / 10volts = 4.1amps Numbers rounded 17

  30. Richard Holt – Rutherford Appleton Laboratory Combined SP & DC-DC powering options November 2008 Detector power efficiency Serial powering a stave, (no DC-DC version) 1 stave = 24 hybrids = 480 ABC-N (0.13 m) Power (constant current) 5.1 Watts 0.5 Watts 52 Watts 14 Watts (70% efficiency ) H 32 Watts Efficiency = 62% D Cables assumed to be 2 ohms total for each power line pair Regulator power = (1/eff - 1) x ABC power H Stave supply current = (32 + 14)watts / (1.2volts x 24) = 1.6amps Numbers rounded 18

  31. Richard Holt – Rutherford Appleton Laboratory Combined SP & DC-DC powering options November 2008 Detector power efficiency Serial powering a stave, (higher voltage, with DC-DC version) 1 stave = 24 hybrids = 480 ABC-N (0.13 m) Power (constant current) 2.4 Watts 0.5 Watts 43 Watts 8.5 Watts (79% efficiency ) H 32 Watts Efficiency = 74% D Cables assumed to be 2 ohms total for each power line pair Regulator power = (1/eff - 1) x ABC power H Stave supply current = (32 + 8.5)watts / (1.6volts x 24) = 1.1amps Numbers rounded 19

  32. SP and Endcap Geometries The baseline design for the endcap of an upgraded ATLAS strip detector is based around petals. Not all hybrids have the same number of chips Group hybrids with similar numbers of chips into their own power chains Chain 1: (3*16) chip units Chain 2: (4*12)+(2*10) chip units Additional current corresponding to two chips must be dissipated by the shunt(s) on each 10 chip hybrid. Efficiency depends upon the values of the analogue and digital voltages and the means used to generate them: Example: 3 ohm cable pair, 1.5V supply, 140mA per chip and 85% shunt efficiency => 54% efficiency GOOD ENOUGH

  33. SP Module Architecture • Module Controller Chip (MCC) • Functions common to SP & DC-DC • multiplexes 2 data streams into 1 • voltage monitoring • Additional for SP • powered by SP • AC coupling of CLK & COM • Requires 4 capacitors • Everything else on chip • Temperature • read by (stave end) DCS • Monitor T before power applied • Shunt protection • under DCS control • Turn on modules independently SP extras SP requires minimal extra circuitry at the module end

  34. Thirty Module Stave: Some Results Occupancy Threshold (mV) Scan point Channel number VT50 (mV) Gain (mV/fC) Input Noise (ENC) Output Noise (mV) Channel number Input Noise (ENC) S-curve

  35. Richard Holt – Rutherford Appleton Laboratory SPi test results September 2009 Example tests Data communication + Works reliably + Can change direction + Can change drive current 50 MHz clock, Showing LVDS inputs and outputs 3.65 ns delay

  36. Richard Holt – Rutherford Appleton Laboratory SPi test results September 2009 Example tests Current measurement + Works reliably - Not perfectly linear

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