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ATLAS SCT Power Supply System

ATLAS SCT Power Supply System. Peter W Phillips STFC Rutherford Appleton Laboratory On behalf of the ATLAS SCT collaboration. SCT Layout. ENDCAP A: 988 modules distributed between 9 disks BARREL: 2112 modules distributed between 4 barrels

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ATLAS SCT Power Supply System

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  1. ATLAS SCTPower Supply System Peter W Phillips STFC Rutherford Appleton Laboratory On behalf of the ATLAS SCT collaboration

  2. SCT Layout Peter W Phillips, TWEPP, Prague, 6th September 2007 • ENDCAP A: 988 modules distributed between 9 disks • BARREL: 2112 modules distributed between 4 barrels • ENDCAP C: 988 modules distributed between 9 disks • TOTAL: 4088 modules • The desire to provide each module with a single reference potential resulted in the adoption of a single, multi-wire, shielded cable to each module and hence in the location of floating, programmable LV and HV power supply channels together in each PS crate.

  3. SCT Detector Modules SCT Barrel Module All modules have similar electrical requirements before irradiation: • 12 ABCD3T readout ASICs (together): • Vcc 3.5V, 900mA typical • Vdd 4.0V, 570mA typical • Includes contribution from opto readout ASICs, DORIC and VDC • RESET, 0 or Vdd • SELECT, 0 or Vdd • 2 to 4 silicon sensors: • HVBIAS, 150V, ~100nA typ. • Current strongly T dependent • Bias for optoelectronic readout: • VPIN, 6V typical • VVCSEL, 4V typical • Temperature Monitoring • Barrel module has 2 10k NTC • Endcap module has 1 10k NTC Effects of radiation: • LV power ~ constant • Idd up but Icc down • Voltages may need to be increased • HV power increases • Voltage from 150V to 500V • Current from ~100nA to 5mA • Optoelectronics • Increased bias voltages Peter W Phillips, TWEPP, Prague, 6th September 2007 SCT Endcap Outer Module

  4. SCT PS Rack • Power Pack Shelf • 4 commercial 48V DC packs • Output power 2kW each • Output current 42A each • 3 packs needed to power rack • 4th pack gives redundancy • Circuit Breaker Box • Power Pack Monitor card (PPM) • Uses ELMB card based on AtMega 128L processor • Monitors status of power packs and fan trays • 12 Miniature Circuit Breakers (MCBs) • Feed 48V DC to the PS crates • 3 MCBs per crate (backplane segmented) • 2 Heat Exchangers • 4 PS Crates • 4 Fan Trays Peter W Phillips, TWEPP, Prague, 6th September 2007

  5. SCT PS Crate Custom Backplane • 48 D17W5 connectors • module power outputs • 1 D25 connector • interlock inputs • 8 screw terminals • power input A custom 6U crate providing power for up to 48 SCT detector modules: Peter W Phillips, TWEPP, Prague, 6th September 2007 Crate Controller 12 x SCTLV 6 x SCTHV SCT Shorting Card SIC: SCT Interlock Card

  6. SCTHV Card The SCTHV card has 8 channels, each with its own ADmC812 processor. An additional processor handles communication between the channels and the crate backplane. • Channel Outputs: • HV, 0-500V • Programmable over current trip • 5mA max Power is input to each LV / HV card at 48V DC. An oscillator block is used to modulate this such that each channel is isolated from ground by means of a transformer. Power at 5V for the SIC, CC and power card master processors is generated by a commercial DC-DC converter housed in the crate. Peter W Phillips, TWEPP, Prague, 6th September 2007 Cracow IFJ

  7. SCTLV Card The SCTLV card has 4 channels. Each channel comprises two blocks, each with its own ADmC812 processor. An additional processor handles communication between the sub-channels and the crate backplane. • Analogue Sub-channel • Vcc, 0-10V, 1.3A max • 80 mA i source for NTC1 • 80 mA i source for NTC2 • Digital Sub-channel • Vdd, 0-10V, 1.3A max • VPIN, 0-10V, 10mA max • VVCSEL, 0-6.6V, 1mA max • RESET, 0 or Vdd • SELECT, 0 or Vdd • Current trips or limits implemented for all voltage outputs • Remote sensing provided for high current lines (Vcc, VccRet, Vdd, VddRet) • Programmable over temperature trip using the module’s NTC thermistors Peter W Phillips, TWEPP, Prague, 6th September 2007 Institute of Physics, ASCR, Prague

  8. SCT PS Crate Controller The Crate Controller is also based around the ELMB card. Its main functions are: • Communication inside a crate • Custom 8 bit parallel bus • Communication outside a crate • CAN bus • Non volatile memory • Stores channel set points for three states: OFF, STB, ON • Transition requests do not need to be accompanied by data: FASTER! • Stores mapping of channels to cooling structures • Transition request for all modules of one cooling structure is reduced to one command per crate • Control • Set data is retrieved from non-volatile (or volatile) memory to set a channel or group of channels to a predefined state (or manual) • Monitoring • Read cards, data to CAN • Detector Safety • Over T “Soft” trip • Turn off LV and HV • HV over current “soft” trip • Turn off HV only Peter W Phillips, TWEPP, Prague, 6th September 2007 Cracow IFJ

  9. SCT Interlock System SCT Interlock Matrix • Located in the SCT DCS rack • Inputs derived by discrimination of signals from thermistors mounted on detector cooling structures • ispMach 5000VG series CPLD maps these signals to PS channels so power can only be applied to cooled structures • Additional IO from ATLAS DSS • One unit (of final 8) shown SCT Interlock Card (SIC) • One in each PS crate • Inputs from the Interlock Matrix • Opto isolation provided • Outputs to PS crate backplane • 12 LV/HV enable lines • one for each group of 4 channels • 1 VCSEL enable line • enables VCSEL voltage output (and hence on detector VCSEL laser diodes) for the entire crate Peter W Phillips, TWEPP, Prague, 6th September 2007 Uppsala University

  10. SCT Power Distribution PS CRATE PP3 Peter W Phillips, TWEPP, Prague, 6th September 2007 Type IV Cu Cable, <100m • Considerations: • Minimise mass in the detector volume • Keep voltage drops within acceptable limits • In addition to common mode filtering, PP3 includes voltage limiters. ABCD is not a constant current design, and damage may occur if too much voltage is applied to the chips • Cost Type III Cu Cable, <25m In-line Splice (PP2) Type II Cu Cable, Barrel: <7m Endcap: <5m Type 0 Cu/Kapton Power Tape Type I Cu/Kapton Power Tape PPF0 Endcap: PPF1 Barrel: PPB1 Module Barrel: Type I Low Mass Tape, Aluminium/Kapton (50um Al)

  11. Cable Installation Cables must be installed to precise tolerances 4088 cable chains • 20440 connectors • 347480 active pins • Lots of testing • Occasional repairs • HARD WORK! Peter W Phillips, TWEPP, Prague, 6th September 2007 Locating Type II Cables using dummy PPB1 Eight rows of correctly installed Type II cables D17W5 connector: 3 per cable chain!

  12. Peter W Phillips, TWEPP, Prague, 6th September 2007 Cryostat Flange viewed from side A after installation of EC-A, showing routing of 2044 (red) Type II SCT Power Cables To USA15 To US15

  13. Early Experiences Production PS hardware and software used successfully during macroassembly • Liverpool (ECC) • NIKHEF (ECA) • Oxford (BAR) • Complete B6 powered and read out (2005) - 14 crates • CERN SR1 (all) • Barrel Sector (SCT+TRT) cosmic test • N.B. “test” cables used for these tests, not the full cable chain… SCT PS PVSS project continued to evolve through this period • Core functionality good • Based around three state model OFF / STB / ON • Control parameters stored in CC ELMB non-volatile memory • DDC link available for DAQ – DCS communication (commands and data) • Geographical mapping information stored using aliases • Some important limitations: • Single PC, no more than 14 crates • No FSM • Channel grouping for control possible, but limited to 8 groups • These limitations have all been addressed in the final system Peter W Phillips, TWEPP, Prague, 6th September 2007

  14. US15 PS Hardware 11 SCT PS Racks Total of 22 Barrel crates Total of 22 Endcap crates 1 SCT DCS Rack Interlock Matrices Can BUS power 5 LCS PCs 2 Barrel 2 Endcap 1 Common Environment 10 CAN buses 8 for PS crates 2 for PPM cards USA15 PS Hardware 11 SCT PS Racks Total of 22 Barrel crates Total of 22 Endcap crates 1 SCT DCS Rack Interlock Matrices Can BUS power 5 LCS PCs 2 Barrel 2 Endcap 1 Common Environment 1 SCS PC High Level Control 9 CAN buses 8 for PS crates 1 for PPM cards Hardware in the ATLAS PIT Peter W Phillips, TWEPP, Prague, 6th September 2007

  15. Mapping and Grouping issues • For control purposes, modules need to be grouped according to the physical cooling structures • Facilitates the continued operation of the detector in the event of loss of one cooling circuit • Restricted space => limitations on cable routing • Possible to route adjacent bundles of cables to different off detector locations, but not at the single channel level • Need a high “packing factor” for the crates • Endcap disk/quadrants generally split between crates to minimise unused channels • Endcap rings have 10 or 13 modules per quadrant: not well matched to the interlock modularity of 4 channels • Where possible, channels shuffled around to minimise the number of cases where one interlock group (LV card) services modules from more than one cooling structure • Several barrel loops cross the cavern boundary • Control software (PVSS) needs to be able to combine channels into groups across multiple host computers Peter W Phillips, TWEPP, Prague, 6th September 2007

  16. FSM Hierarchy SCT Subdetector ECA BAR ECC TTC Partitions Peter W Phillips, TWEPP, Prague, 6th September 2007 ENV PPM PS ROD Subsystems Quadrants Q1 Q2 Q3 Q4 PC: ATLSCTSCS PC: ATLSCTUSABPS1 PC: ATLSCTUSBPS1 Loop_B306 Crate_84_B306 Crate_00_B306 …… …… Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel (36) (12)

  17. FSM: SCT Loop Status Peter W Phillips, TWEPP, Prague, 6th September 2007 ECA: 36 loops BAR: 44 loops ECC: 36 loops

  18. B306 FSM: SCT Barrel Loop Status Peter W Phillips, TWEPP, Prague, 6th September 2007 As viewed from C side. Split into quadrants according to cooling structures.

  19. Mapping Issues: Barrel Each Barrel cooling loop serves 48 modules, not necessarily powered by the same PS crate, or even by crates in the same service cavern. Example: Barrel 3 Loop 6 Peter W Phillips, TWEPP, Prague, 6th September 2007 36 modules powered from USA15, Crate 84 12 modules powered from US15, Crate 00

  20. Mapping Issues: Endcap Peter W Phillips, TWEPP, Prague, 6th September 2007 16 modules powered By Crate 49 17 modules Powered By Crate 79

  21. FSM Hierarchy SCT Subdetector ECA BAR ECC TTC Partitions Peter W Phillips, TWEPP, Prague, 6th September 2007 ENV PPM PS ROD Subsystems Quadrants Q1 Q2 Q3 Q4 PC: ATLSCTSCS PC: ATLSCTUSABPS1 PC: ATLSCTUSBPS1 Loop_B306 Crate_84_B306 Crate_00_B306 …… …… Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel (36) (12)

  22. FSM: Combined Channel States The main operational states: • OFF • LV hardware OFF • HV hardware OFF • Cannot read module temp. • INITIAL • LV OFF (0V / 0V) • HV OFF (5V) • Can read module temperature • STARTING • LV STB (2.5V / 3.0V) • HV STB (50V) • Reduces probability of over current trips (Icc, Idd) during power on • STANDBY • LV ON (3.5V / 4.0V) • HV STB (50V) • Reduced detector bias: used during (moderately) unstable beam conditions • ON • LV ON (3.5V / 4.0V) • HV ON (150V) • “OK FOR PHYSICS” Error States Operational States Peter W Phillips, TWEPP, Prague, 6th September 2007 DISABLED OFF MANUAL INITIAL UNKNOWN RAMPING NO_MATCH STARTING TRIP_LV TRIP_BOTH RAMPING STANDBY TRIP_HV RAMPING INTERLOCKED ON

  23. FSM: Quadrant, Loop and Group States The states of all children are combined such that: • If any children are in error states • The most significant error is reported • If no children are in error states • The highest state of any child is determined • If the full complement of children are in that state, the corresponding complete state will be reported • For example, ON • If less than the full complement of children are in that state, the corresponding partial state will be reported • For example, ON_PART Peter W Phillips, TWEPP, Prague, 6th September 2007 ON ON_PART RAMPING STANDBY STANDBY_PART RAMPING STARTING_PART STARTING RAMPING INITIAL_PART INTIAL OFF Only operational states shown: there are additional error states, e.g. INTERLOCKED

  24. PS GOTO_INITIAL For all cooled loops Monitor temperatures GOTO_STARTING GOTO_STANDBY LV at operational values Corrective actions Reset, power cycle etc GOTO_ON Detector bias to operational values DAQ BOOT CONFIGURE Next PS operation may fail if modules not clocked Configure Modules Send configuration packets Probe modules Send L1A and trap events Corrective Actions Re-send configuration etc. START READY FOR PHYSICS! Operational Model Peter W Phillips, TWEPP, Prague, 6th September 2007

  25. Detector Safety Safety trips at many levels to prevent over heating or over current: • LV / HV firmware • LV channel over current (Icc, Idd) • LV channel programmable over temperature trip • Uses on-module thermistors; maximum set point value 38C • HV channel programmable over current trip • HV channel over voltage trip • LV card over temperature trip • Protects LV card itself from damage caused by overheating • Crate Controller Software • Over temperature trip • Switches off both LV and HV • Set to act before LV card firmware • HV over current trip • Gentle ramp down of HV only • Set to act before HV card firmware • PVSS Software • Do not allow module power to be applied if cooling loop not running • Shutdown all modules of one loop if cooling loop fails • Shutdown all modules if cooling plant shutdown • Hardware Interlock • Trip off all modules of one cooling segment if pipe temperature exceeds preset limit (potential divider) Peter W Phillips, TWEPP, Prague, 6th September 2007

  26. Summary • ATLAS SCT uses 4088 programmable, independent and floating HV and LV power supply channels distributed between 88 crates. • Installation of so many cable chains to precise tolerances with full connectivity a time consuming task, but was managed well. • The high level software groups channels together by cooling circuit, and then cooling circuits are grouped into quadrants. This matches the structure of the cooling system and its controls. • Small improvements continue to be introduced to the system, however the core functionality is working well. • The system has been used during commissioning tests of all three TTC partitions, and the SCT PS FSM has been integrated into the central ATLAS DCS. • The ATLAS SCT Power Supply System is essentially ready for physics! Peter W Phillips, TWEPP, Prague, 6th September 2007

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