Sequential Circuits : Part I

1. Sequential Circuits : Part I Read Sections 5-1, 5-2, 5-3

2. Topics • Sequential Circuits • Latches • Flip Flops

3. Sequential Circuits • Definition: State of system is “stored information” • Present state and inputs, determine outputs and next state

4. Types of Sequential Circuits • Synchronous • State changes are synchronized by one or more clocks • Asynchronous • Each state change occurs independently of other changes

5. Clocking of Synchronous • Changes of the state enabled by a clock

6. Comparison • Synchronous • Easier to analyze • Choose the clock so that changes are only allowed to occur before next clock pulse • Asynchronous • Potentially faster • Harder to analyze • Will look mostly at synchronous

7. YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES ____________________________________ Fig. 5-2 Logic Structures for Storing Information Basic Storage

8. YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES YES.YESYESYESYESYESYESYESYESYESYESYES ____________________________________ Fig. 5-2 Logic Structures for Storing Information Basic Storage • Apply low or high for longer than tpd • Feedback will hold the value of the input

9. ____________________________________ Fig. 5-2 Logic Structures for Storing Information Basic Storage • Apply low or high for longer than tpd • Feedback will hold the value of the input

10. Fig. 5-4 SR Latch with NOR Gates SR (set-reset) Latches • Basic storage made from gates • Requirement: outputs be the complements of each other • S & R both 0, Latch in “resting” state • Have to keep both from 1 at same time

11. When both S and R go to 0 after 11, Q & Q_b take on unknown values; depends on circuit delays and slight differences in the times at which S & R change values Simulation Of SR Behavior

12. YES. yes. YES.YES.YES.YES.YES. YES YES. YES. yes. YES.YES.YES.YES.YES. YES YES. YES. yes. YES.YES.YES.YES.YES. YES YES. Latch

13. Latch

14. Good Morning. Good Morning. Good Morning. Good Morning Add Control Input (SR ) • Input, C, controls when state can change

15. Add Control Input (SR ) • Input, C, controls when state can change • Is there a latch with no undefined state?

16. D-type Latch • No undefined (illegal) state

17. D-type Latch • No undefined (illegal) state

18. Flip-Flops • Two major types • Master-Slave • Two stage • Output not changed until clock disabled (low) • Edge triggered • Change happens when clock level changes

19. Master Latch Slave Latch Master-Slave Flip-Flop • Either master or slave is enabled, not both

20. Illegal State (a) Q should be 0 since Q was 0 before the clock pulse and both S & R are 0 just before the clock goes to 0 (b) FF in wrong state due to 1’s catching Timing Diagram

21. Note: • New inputs appear at latches are not sent to output until clock low • Changes at input of FF when clock high trigger next state

22. D-Type Positive-Edge Triggered FF

23. Standard Symbols for Storage Elements S S D D R R C C D with 0 Control SR D with 1 Control SR (a) Latches S S D D C C R R C C Triggered D Triggered D Triggered SR Triggered SR (b) Master-Slave Flip-Flops D D C C Triggered D Triggered D (c) Edge-Triggered Flip-Flops • Master-Slave:Postponed outputindicators • Edge-Triggered:Dynamicindicator

24. Direct Inputs • Set/Reset independent of clock • Direct set or preset • Direct reset or clear • Often used for power-up reset

25. Next • State Diagrams • Registers