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High-Performance Continuous-Time MASH Sigma-Delta ADCs for Broadband Wireless Applications

Discover the design principles and operation of CT-MASH Sigma-Delta modulators for high-performance ADCs in broadband wireless applications. Learn about key features, architecture, calibration techniques, and measurement results to enhance receiver sensitivity with low power consumption.

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High-Performance Continuous-Time MASH Sigma-Delta ADCs for Broadband Wireless Applications

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  1. High-Performance Continuous-Time MASH Sigma-Delta ADCs for Broadband Wireless Applications Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Negar Rashidi, and Jose Silva-Martinez Texas A&M University Department of ECE

  2. Outline • Introduction • Sigma-Delta Modulator • CT-MASH Sigma-Delta Modulator • Design Examples • Sigma-Delta ADC with 7-bit Quantizer and Fully Digital MASH Algorithm • MASH ADC with Fully Integrated Quantization Noise Leakage Calibration • Summary • Reference

  3. Smartphone standards evolution Standards constantly evolve. LTE advance peak rate ~10-300Mbps Jose Silva-Martinez

  4. Important Features for ADCs • High bandwidth (>50 MHz) • Carrier aggregation • Full band capture • High resolution (>10 bit) • Presence of blockers requires higher dynamic range • Sensitivity of receiver • Low power consumption • Extent battery life for mobile receivers. Jose Silva-Martinez

  5. Introduction: Carrier Aggregation LTE receiver: ADC bandwidth > 10 MHz LTE-Advanced receiver: ADC bandwidth > 50 MHz

  6. Sigma-Delta Modulator Oversampling ADC + Closed-Loop Noise Shaping: NTF STF Sigma-Delta Modulator Concept

  7. Single Loop vs MASH ΣΔModulator Single-Loop 2nd Order MASH 1-1 • Single-Loop SDM: • Cons: • Stability problem for high order loops • SQNR sacrificed due to OOB noise E1 • MASH: • Pros: • No potential stability problem • Good overload recovery • Better SQNR (tolerate more OOB noise) • Cons: • Need to match digital-based NCF with analog-based NTF in CT-MASH

  8. MASH ΣΔModulator Leslie-Singh; ISCAS 1990 Analog Intensive MASH topology DAC Schreier-Temes Book

  9. Carlos Briseno-Vidrios MASH 4-0 ΣΔModulator: Architecture ΣΔADC with 7-bit Quantizer and Fully Digital MASH Algorithm [2] MASH 4-0 Architecture: • Single 7-bit quantizer, only 4 bits in the loop • Any loop architecture can be used, the improvement depends on extra bits of Quantizer and Algorithm

  10. MASH 4-0 ΣΔModulator: Algorithm ΣΔADC with 7-bit Quantizer and Fully Digital MASH Algorithm [2] Frequency domain implementation: NTFAD is saved in to memory, and used as a digital filter in the frequency domain

  11. MASH 4-0 ΣΔModulator: Operation ΣΔADC with 7-bit Quantizer and Fully Digital MASH Algorithm [2] NTFAD calculation: • Apply the FFT to the signal ADC’s outputs • Apply division bin by bin • Save on to Look up table

  12. Carlos Briseno-Vidrios MASH 4-0 ΣΔModulator: Operation ΣΔADC with 7-bit Quantizer and Fully Digital MASH Algorithm [2] Real time data cancellation: • Apply the FFT to the signal ADC’s outputs • Used the saved NTFADto obtain YOUT • Update NTFADforPVT robustness

  13. Carlos Briseno-Vidrios MASH 4-0 ΣΔModulator: Measurement ΣΔADC with 7-bit Quantizer and Fully Digital MASH Algorithm [2] Details: • Chip fabricated in 130 nm • Total power consumption from ADC 20 mW. • Satisfactory NTFADmeasurement

  14. Carlos Briseno-Vidrios MASH 4-0 ΣΔModulator: Measurement ΣΔADC with 7-bit Quantizer and Fully Digital MASH Algorithm [2] Briseno-Vidrios, JSSC, Jun. 2016 After algorithm: • Cancellation limited by thermal noise (6 dB) • Higher frequency cancellation improves (12 dB) • Constant cancellation for different inputs

  15. Carlos Briseno-Vidrios MASH 4-0 ΣΔModulator: Measurement ΣΔADC with 7-bit Quantizer and Fully Digital MASH Algorithm [2] Briseno-Vidrios, JSSC, Jun. 2016 *C. Briseno-Vidrios, et.al., " A 4-Bit Continuous-Time Σ∆ Modulator with Fully Digital Quantization Noise Reduction Algorithm Employing a 7-Bit Quantizer," June 2016, IEEE J. of Solid-State Circuits.

  16. MASH 2-2 ΣΔModulator: Architecture MASH ADC with Fully Integrated Quantization Noise Leakage Calibration [3] MASH 2-2 Architecture: • Proper architecture with feedforward paths [4] • Use of high-accuracy RC calibration • Use of a high performance operational amplifier A. Edward, JSSC, April 2017

  17. MASH 2-2 ΣΔModulator: RC Calibration A. Edward, JSSC, April 2017 MASH 2-2 RC Calibration: • Calibrated at start-up • Digital code controlling the switchable loop filter capacitors • Comparing the rise time of a ramp waveform generated by a replica integrator charged with the DAC current with reference rise-time

  18. MASH 2-2 ΣΔModulator: Operational Amplifier MASH ADC with Fully Integrated Quantization Noise Leakage Calibration [3] Av > 60dB at 50MHz

  19. MASH 2-2 ΣΔModulator: Microphotograph MASH ADC with Fully Integrated Quantization Noise Leakage Calibration [3]

  20. MASH 2-2 ΣΔModulator: Measurement MASH ADC with Fully Integrated Quantization Noise Leakage Calibration [3]

  21. Comparison with State-of-the-Art CT-MASH Modulators with BW > 10MHz )

  22. MASH CT ΣΔModulator MASH 1-1 CT ΣΔ Modulator Qiyuan: Journal paper under evaluation MASH 1-1-1

  23. MASH 1-1-1 CT ΣΔModulator

  24. Summary • Fundamentals on MASH modulators • CT-MASH architecture synthesis • Design Examples • CT-MASH 4-0 fabricated in 130 nm CMOS consumes 20 mW and achieves 75 dB peak SNDR over a 15 MHz badwidth with an active area of 1.3 mm2 • CT-MASH 2-2 fabricated in 40 nm CMOS show peak SNDR of 74.4 dB within the signal bandwidth of 50.3 MHz with power consumption of 43.0 mW and active area of 0.265 mm2

  25. Reference • [1] M. Keller, A. Buhmann, F. Gerfers, M. Ortmanns, and Y. Manoli, “On the implicit anti-aliasing feature of continuous-time cascaded sigma-delta modulators”, IEEE Trans. Circuits. Syst. I, Reg. Papers, vol. 54, no. 12, pp. 2639–3645, Dec. 2007. • [2] C. Briseno-Vidrios, A. Edward, N. Rashidi, and J. Silva-Martinez, “A 4 bit continuous-time ΣΔ modulator with fully digital quantization noise reduction algorith employing a 7 bit quantizer,” IEEE J. Solid-State Circuits, vol. 51, no. 6, pp. 1398-1409, Jun. 2016. • [3] A. Edward, Q. Liu, C. Briseno-Vidrios, M. Kinyua, E.G. Soenen, A.I. Karsilayan, and J. Silva-Martinez, “A 43-mW MASH 2-2 CT ΣΔ modulator attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 448–459, Feb. 2017. • [4] M. Ortmanns, F. Gerfers, and Y. Manoli, “A case study on a 2-1-1 cascaded continuous-time sigma-delta modulator,” IEEE Trans. Circuits. Syst. I, Reg. Papers, vol. 52, no. 8, pp. 1515–1525, Aug. 2005.

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