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HDL Bencher from Xilinx

HDL Bencher from Xilinx creates timing-constrained VHDL and Verilog testbenches without HDL or scripting knowledge. Validate design function & performance, generate design-specific waveforms, and documentation. Easily simulate with various simulators.

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HDL Bencher from Xilinx

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  1. HDL Bencher from Xilinx • Creates timing constrained VHDL and Verilog self-checking testbenches • No knowledge of HDL or scripting required EE514

  2. Overview • HDL Bencher helps validate design function and performance • HDL Bencher generates • VHDL or Verilog testbenches • Design specific waveforms • Documentation • Testbenches can be simulated with various simulators • Model Technology • Synopsys EE514

  3. How It Works • Step 1: Create New Source • Step 2: Draw stimulus and response waveforms • Step 3: Export testbench EE514

  4. Create a New Source EE514

  5. HDL Bencher • Unit under test is analyzed, when selected • Port problems • Syntax violations • Inconsistencies • Design timing selected • Clocked or combinatorial? EE514

  6. Title bar Process bar Port direction Line numbers Menu Waveform window Waveforms HDL source editor HDL Bencher Windows EE514

  7. Create Waveforms • Data values • 1, 0 ,X ,Z, U • Assignments • Double-click bit signal to toggle value • Pattern wizard assigns a range of cell values • WaveTable assigns signals like a spreadsheet • By default, decimal values are shown in the WaveTable • Waveform values are checked as they are entered • Validation check for non-binary inputs only (for example, hex, or decimal) EE514

  8. Toggling • Toggling bit values is the easiest way to assign bit signals • Simply click directly on the signal’s waveform at the time where changes should take place Click directly on these boxes, at the time where signals should toggle EE514

  9. Double-click in this area Enter values in this area WaveTable • Intended for fast behavioral verification • Waveforms represented as cells • Data entered in spreadsheet format • Double-click a signal at the time it should be changed, to access value cell editor • Enter value and press Return for the next time frame • Range validation checked after each entry EE514

  10. Pattern Wizard • Aids complex waveform input • To access, click a signal at the time it should be changed to access value cell editor • Note: light blue background = input assignment, • light yellow background = output assignment Click in this area Click here for Pattern Wizard EE514

  11. Available patterns Pattern description Changes depending on the pattern selected Count unit in clock cycles Pattern Wizard EE514

  12. Export Testbench • Translates waveforms to testbenches • Writes out VHDL or Verilog testbench • Color-coded for easy reading and reference • Includes • Library extractions • Log file creation • Procedure check • Input assignments • Output validation • Defined test signals • Delay verification • UUT (Unit Under Test) instantiation EE514

  13. File extensions Export Testbench Configuration VHDL compliance • Generated Testbench extensions are .vhd or .v • Usually have “_tb” in the file name • Generated Waveform file extensions are .tbw Ability to automatically terminate the testbench for export on the last assignment EE514

  14. Summary • HDL Bencher helps validate design function and performance • The three steps to create a testbench are • Create a new source • Develop waveforms • Export testbench • Writes out VHDL or Verilog testbench EE514

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