80386 AND PENTIUM MICROPROCESSORS

1. 80386 AND PENTIUM MICROPROCESSORS Dr.P.Yogesh, Senior Lecturer, DCSE, CEG Campus, Anna University, Chennai-25.

2. Evolutionary Offspring of 8086/8088 Microprocessors 8086/8088 is the simplest member of 80x86 family However there are many other powerful offspring of 8086 microprocessor which are used in the industry heavily 80186 is basically an 8086 with an on-chip pritority controller, programmable timer, DMA controller and address decoding circuitry This processor has been mostly used in industrial control applications

3. Evolutionary Offspring of 8086/8088 Microprocessors The 80286, another 16 bit enhancement of 8086 has the features like virtual management circuitry, protection circuitry and a 16-MByte addressing capability The 80286 was the first family member designed specifically for use as the CPU in a multiuser microcomputer The needs of a multitasking/multiuser operating system include environment preservation during task switches, operating system and user protection and virtual memory management system 808286 is the first 80x86 family microprocessor designed to implement these features relatively easy

4. Evolutionary Offspring of 8086/8088 Microprocessors Moreover the 80286 was the microprocessor used as the CPU in IBM PC/AT and its clones The 80286 can operate in one of the two memory address modes, real address mode or protected virtual address mode In the real address mode, the address unit computes addresses using a segment base and an offset just as the 8086 does In the protected virtual address mode (protected mode), 80286 uses all 24 address lines to access up to 16Mbytes of physical memory In protected mode it also provides up to a gigabyte of virtual memory.

5. Evolutionary Offspring of 8086/8088 Microprocessors Some of the limitations of the 80286 microprocessor are that it has only a 16-bit ALU, its maximum segment size is 64 Kbytes and it can not easily be switched back and forth between real and protected modes These drawbacks are eliminated in 32-bit microprocessors

6. 32 bit Processors 32 bit microprocessors are not merely more of the same except bigger and faster They offer some unique features not available in earlier 16-bit processors

7. 32 bit Processors They satisfy some major requirements of multitasking/multiuser systems like higher speed of execution ability to handle different types of tasks efficiently, large memory space that can be shared by multiple users appropriate memory allocations and the management memory access, data security and data access etc

8. 32 bit Processors Some of these requirements must be managed by a multiuser operating system, and some should be facilitated by the architectural design of the microprocessors 32-bit microprocessors and 64 bit microprocessors have been designed and implemented to meet these requirements

9. 80386 Microprocessor The 80386 is an advanced 32-bit microprocessor optimized for multitasking operating systems and designed for applications needing very high performance 80386 maintains the software compatibility with 80286. The 32-bit registers and data paths support 32-bit addresses and data types

10. 80386 Microprocessor The processor can address up to four gigabytes of physical memory and 64 terabytes (2 ^ (46) bytes) of virtual memory 80386 segments can be as large as 4 Giga Bytes and a program can save as many as 16384 segments. The virtual address then is 16384 segments * 4 GBytes, or about 64TBytes

11. 80386 Microprocessor The 80386 has a virtual mode which allows it to easily switch back and forth between 80386 protected mode tasks and 80386 real mode tasks The on-chip memory-management facilities of 80386 include address translation registers, advanced multitasking hardware, a protection mechanism, and paged virtual memory Special debugging registers provide data and code breakpoints even in ROM-based software

12. Operating Modes The 80386 has three processing modes 1. Protected Mode 2. Real-Address Mode 3. Virtual 8086 Mode.

13. Operating Modes Protected mode is the natural 32-bit environment of the 80386 processor In this mode all instructions and features are available

14. Operating Modes Real-address mode (often called just "real mode") is the mode of the processor immediately after RESET In real mode the 80386 appears to programmers as a fast 8086 with some new instructions Most applications of the 80386 will use real mode for initialization only

15. Operating Modes Virtual 8086 mode (also called V86 mode) is a dynamic mode in the sense that the processor can switch repeatedly and rapidly between V86 mode and protected mode

16. Programming Model of 80386 The basic programming model of 80386 consists of Memory organization and segmentation Data types Registers Instruction format Operand selection Interrupts Exceptions

17. Memory Organization and Segmentation A "flat" address space consisting of a single array of up to 4 gigabytes A segmented address space consisting of a collection of up to 16,383 linear address spaces of up to 4 gigabytes each

18. Memory Organization and Segmentation

19. Memory Organization and Segmentation 1. A segment selector, which is a 16-bit field that identifies a segment. 2. An offset, which is a 32-bit ordinal that addresses to the byte level within a segment.

20. Data Types

21. Data Types

22. Data Types Ordinal Near Pointer Far Pointer String Bit field Bit string BCD Packed BCD

23. Data Types

24. Data Types

25. Data Types

26. Data Types

27. Data Types

28. Registers General registers. These eight 32-bit general-purpose registers are used primarily to contain operands for arithmetic and logical operations. Segment registers. These special-purpose registers permit systems software designers to choose either a flat or segmented model of memory organization. These six registers determine, at any given time, which segments of memory are currently addressable. Status and instruction registers. These special-purpose registers are used to record and alter certain aspects of the 80386-processor state.

29. General Registers

30. Segment Registers

31. Status and Instruction Registers

32. Memory Segmentation

33. Stack

34. Flags

35. Flags Carry Flag: Set in math instructions to indicate that the high-order bit was either carried or borrowed. It is cleared if neither of these conditions occurs. Parity Flag: Indicates whether the lower 8-bits of a result contains an even number of bits set to 1 (flag is set) or an odd set of bits are set to 1 (flag is cleared) Adjust Flag: Set in decimal math instructions to indicate whether the low order 4-bits of AL where carried, or borrowed. It is cleared if not.

36. Flags Zero Flag:Set to indicate a math instruction resulted in a zero result. It is cleared otherwise. It is also used by string and loop instructions to indicate completion of the instruction. Sign Flag:Set equal to high-order bit of results of math instruction. If set the result is negative, positive if cleared. Overflow Flag:Indicates if the number placed in the destination operand overflowed, either too large, or small. If no overflow occurred, the bit is cleared.

37. Instruction Pointer

38. Instruction Format The elements of an instruction, in order of occurrence are as follows Prefixes Opcode Register specifier Addressing-mode specifier SIB (scale, index, base) byte Displacement Immediate operand

39. Operand Selection In the instruction itself (an immediate operand) In a register (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP in the case of 32-bit operands; AX, BX, CX, DX, SI, DI, SP, or BP in the case of 16-bit operands; AH, AL, BH, BL, CH, CL, DH, or DL in the case of 8-bit operands; the segment registers; EFLAGS register for flag operations In memory At an I/O port

40. Default Segment Register Selection Rules

41. Effective Address Computation

42. Interrupts and Exceptions The 80386 has two mechanisms for interrupting program execution 1. Exceptions are synchronous events that are the responses of the CPU to certain conditions detected during the execution of an instruction. 2. Interrupts are asynchronous events typically triggered by external devices needing attention.

43. Interrupts and Exceptions

44. Interrupts and Exceptions A divide error exception results when the instruction DIV or IDIV is executed with a zero denominator or when the quotient is too large for the destination operand The debug exception may be reflected back to an applications program if it results from the trap flag (TF) A breakpoint exception results when the instruction INT 3 is executed This instruction is used by some debuggers to stop program execution at specific points

45. Interrupts and Exceptions An overflow exception results when the INTO instruction is executed and the OF (overflow) flag is set (after an arithmetic operation that set the OF flag). A bounds check exception results when the BOUND instruction is executed and the array index it checks falls outside the bounds of the array. Invalid opcodes may be used by some applications to extend the instruction set. In such a case, the invalid opcode exception presents an opportunity to emulate the opcode.The "coprocessor not available" exception occurs if the program contains instructions for a coprocessor, but no coprocessor is present in the system. A coprocessor error is generated when a coprocessor detects an illegal operation.

46. I/O Addressing The 80386 allows input/output to be performed in either of two ways By means of a separate I/O address space (using specific I/O instructions) By means of memory-mapped I/O (using general-purpose operand Manipulation instructions)

47. Pentium Processors The term ''Pentium processor'' refers to a family of microprocessors that share a common architecture and instruction set The first Pentium processors (the P5 variety) were introduced in 1993 This 5.0-V processor was fabricated in 0.8-micron bipolar complementary metal oxide semiconductor (BiCMOS) technology

48. Pentium Processors The P5 processor runs at a clock frequency of either 60 or 66 MHz and has 3.1 million transistors The next version of the Pentium processor family, the P54C processor, was introduced in 1994 The P54C processors are fabricated in 3.3-V, 0.6-micron BiCMOS technology The P54C processor also has System Management Mode (SMM) for advanced power management

49. Operating Modes Protected Mode Real Address Mode System Management Mode

50. Features Superscalar Execution Pipeline Architecture Branch Target Buffer Dual 8-KB On-Chip Caches Write-Back Cache 64-Bit Bus Instruction Optimization

51. Features Floating-Point Optimization Pentium Extensions

52. Pentium Architecture