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Test setup for RAL structures - Cedric Mansuy

Test setup for RAL structures - Cedric Mansuy. Test setup ready main board + chip carrier PCBs (2 types: transistors (1), HV transistors, insulation, capacitances (2)) Setup with lab instruments (switching matrix, LCRmeter , source-meters) and Labview Software for analyzing data ( Matlab )

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Test setup for RAL structures - Cedric Mansuy

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  1. Test setup for RAL structures - Cedric Mansuy • Test setup ready • main board + chip carrier PCBs (2 types: transistors (1), HV transistors, insulation, capacitances (2)) • Setup with lab instruments (switching matrix, LCRmeter, source-meters) and Labview • Software for analyzing data (Matlab) See presentations by Cedric in WG3 meetings https://indico.cern.ch/categoryDisplay.py?categId=3308 • Wire bonding of dies not possible due to matrix-structure of the pads >> Au ball bonding with company in Switzerland (Hybrid SA) • 10 carriers with chips mounted and Au ball bonded delivered 29/5/2012

  2. Main board with chip carrier

  3. Chip • 10 chips mounted: • 5.5 um epi without deep p-well • Next carriers equipped with 12 um epi layer and without deep p-well • Connect 1-11 and 10-20 or 11-21 and 20-24

  4. Chip carrier

  5. NMOS transistor (preliminary) Low voltage Ids Vs Vds High voltage

  6. PMOS transistor (preliminary) Ids Vs Vds

  7. Isolation (preliminary) Leakagecurrent Vs voltage

  8. Capacitance (preliminary) Capacitance Vs voltage bias

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