EMT 235 DIGITAL ELECTRONIC PRINCIPLES II

1. EMT 235 DIGITAL ELECTRONIC PRINCIPLES II Sequential Logic Review ~ Preliminary to Chapter 2~ Weeks 4

2. “Combinational” vs “Sequential” • Combinational – outputs depend only on the inputs. • Do not have memory. • Cannot store state. • Sequential – outputs depend on inputs and past behavior. • Require use of storage elements. • Contents of storage elements is called “state”. • Circuit goes through sequence of states as a result of changes in inputs.

3. Overview of Sequential Circuits Storage Elements and Analysis • Introduction to sequential circuits • Types of sequential circuits • Storage elements • Latches • Flip-flops • Sequential circuit analysis • State tables • State diagrams

4. Block Diagram of a Sequential Circuit

5. Sequential Circuit - Basic Function • The data stored in the “storage elements” defines the “state” of the sequential circuit at that time, i.e. present state. • The inputs, together with the present state of the storage elements, determine the outputs and the next state of the storage elements.

6. Types of Sequential Circuits • Depends on the times at which: • storage elements observe their inputs, and • storage elements change their state • Synchronous • Behavior defined from knowledge of its signals at discrete instances of time • Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) • Asynchronous • Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change • If clock just regarded as another input, all circuits are asynchronous!

7. Synchronous Clocked Sequential Circuit

8. Simple Memory Structure

9. Reset Set Q Another Structure for Memory

10. The Most Common Memory Elements Used • Latches • Flip-flops • The basic single-bit memory elements, • With one or two inputs/outputs, • Designed using individual logic gates and feedback loops. • Both are referred to as “bistable elements” or “multivibrator”, i.e. having two stable states.

11. Latches & Flip-flops Part I

12. Latch vs Flip-flop • “The inputs, together with the present state of the storage elements, determine the outputs and the next state of the storage elements.” • Latch • Asynchronous. • Change of statecan happen at any time,whenever its inputs change. • Flip-Flops • Synchronous. • Change of stateoccurs only at specific timesdetermined by a clock pulse input. • Flip-flops are constructed from latches!!

13. Q S C R Q Types of Latches SR Latch Gated D Latch S R Latch Gated SR Latch (with control)

14. S R Latch

15. Reset Set Q SR Latch with NOR Gates Q Re-drawn …

16. SR Latch Function Table Hold Hold

17. … SR Latch Operation • If S=R=0 => the latch is either SET or reSET.. • If S=R=1 => both Q and NQ = 0. • Undefined State!! … violation of Q vs NQ.

18. Simulation of SR Latch .. with delay

19. S-R Latch vs S-R Latch

20. S R Latch

21. Q S R Latch with NAND Gates Active-LOW SR Latch …

22. SR Latch Function Table Hold Hold

23. S R Latch Function Table

24. S R Latch Waveform 1 2 4 3 5 6 7 Assume that Q is initially LOW

25. Q S C R Q Gated SR Latch C or Enable or CLock = SR latch with Control input = SR latch with Enable input = Clocked SR Latch

26. Gated S-R Latch - Basic Operation • A gate input is added to the S-R latch to: - Act as a “control” input. • Make the latch synchronous. • Control=1 => Latch can change state • Control =0 => Latch “holds” previous value

27. Gated SR Latch Function Table Where is the additional circuit?

28. 1 C 0 1 R 0 Q S 1 C S 0 R Q 1 ? Q 0 1 ? Q 0 Time Gated SR Latch Simulation

29. Q D Q C Gated D Latch

30. Gated D Latch Add inverter to the SR latch…

31. Gated D Latch Function Table Note: There are no “indeterminate states” …

32. t t t t 1 2 3 4 Clk D Q Time Gated D Latch Simulation

33. State Change in Latch • Change in latch state => Trigger • The D latch with clock pulses on its Control, C, input is triggered every time a pulse to logic-1 level occurs. • As long as the pulse remains at the logic-1 level, any changes in the data input will change the state of the latch. “Level” triggered

34. Edge-Triggered Flip-flops • Flip-flops are synchronous bistable devices. • Synchronous: because the output changes state ony at a certain point on a triggering input, i.e. CLK, which is the control input. • Edge-triggered flip-flop: changes state at either the positive edge (rising edge) or at the negative edge (falling edge) of the cock pulse.

35. 1 Clock signal 0 Clock Cycle Time Falling edges of the clock (Negative-edge triggered) Rising edges of the clock (Positive-edge triggered) Clock Signals & Synchronous Sequential Circuits • A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

36. Edge-triggered Flip-flop SymbolsPositive edge triggered and Negative edge-triggered • All the above flip-flops have the triggering input called clock (CLK/C)

37. Edge-Triggered Flip-flops • SR flip-flop • JK flip-flop • D flip-flop • T flip-flop

38. Timing Diagram

39. D D S Q Q Q C C C Q R Q Q Negative-Edge Triggered D Flip-Flop • The edge-triggered D flip-flop is thesame as the master-slave D flip-flop. • It can be formed by: • Replacing the first clocked S-R latch with a clocked D latch or • Adding a D input and inverter to a master-slave S-R flip-flop • The delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present with D replacing S and R inputs • The change of the D flip-flop output is associated with the negative edge at the end of the pulse. • It is called a negative-edge triggered flip-flop

40. D D S Q Q Q C C C Q R Q Q Q D Clock Q Positive-Edge Triggered D Flip-Flop • Formed byadding inverterto clock input • Q changes to the value on D applied at the positive clock edge within timing constraints to be specified. • The standard flip-flop used for most sequential circuits.

41. Q D Clock Q (b) Graphical symbol Positive-Edge-Triggered D Flip-Flop 1 P3 P1 2 5 Q Clock 6 Q P2 3 4 P4 D (a) Circuit

42. A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter D CLK/C Q Q’_________________ 1 ↑ 1 0 SET (stores a 1) 0 ↑ 0 1 RESET (stores a 0)

43. Timing Diagram

44. Positive-Edge Triggered JK Flip-Flop • Not used much anymore in VLSI • Advantageous only if using FF chips J Q D Q K Q Q Clock (a) Circuit Q ( t + 1 ) J K 0 0 Q ( t ) J Q 0 1 0 1 0 1 K Q 1 1 Q ( t ) (b) Truth table (c) Graphical symbol

45. Function Table for JK Flip Flop J K CLK Q Q’ 0 0 Q0 Q0’ Hold 0 1 0 1 Reset 1 0 1 0 Set 1 1 Q0’ Q0 Toggle (opposite state)

46. Timing Diagram: Positive-Edge Triggered

47. Timing Diagram: Negative-Edge Triggered

48. Q D Q T Q Q Clock (a) Circuit T Flip-Flop • Useful in counters • Not available in IC form • T Latches do not exist ( ) Q t + 1 T ( ) 0 Q t ( ) 1 Q t (b) Truth table Q T Q (c) Graphical symbol

49. Clock T Q (d) Timing diagram T Flip-Flop

50. D latch vs D flip-flop