Hardware/software Interfacing

Hardware/software Interfacing

Interfacing • Program I/O • Interrupt I/O • Direct Memory Access (DMA) • Device driver

Programming I/O • Two types of instructions can support I/O: • Memory-mapped load/store instructions. • Requires no special instructions • Assembly instructions (load/store) work with peripherals as well • Special-purpose I/O instructions; • No loss of memory addresses to peripherals • Simpler address decoding logic in peripherals possible • When number of peripherals much smaller than address space then high-order address bits can be ignored • smaller and/or faster comparators • Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O. • I/O instructions do not preclude memory-mapped I/O.

memory-mapped I/O • Define location for device: DEV1 EQU 0x1000; device I/O ports • Read/write code: LDR r1,#DEV1 ; set up device adrs LDR r0,[r1] ; read DEV1 LDR r0,#8 ; set up value to write STR r0,[r1] ; write value to device

Address Management • Embedded processor design requires you to manage the following: • Address map for the peripherals • Location of the application code in the memory space • Block RAM • External memory • Memory requirements for your programs are based on the following: • The amount of memory required for storing the instructions • The amount of memory required for storing the data associated with the program

Peek and poke • Traditional interfaces: int peek(char *location) { return *location; } void poke(char *location, char newval) { (*location) = newval; }

Polling • CPU constantly polls the device for its status while (TRUE) { /* read */ while (peek(IN_STATUS) == 0); achar = (char)peek(IN_DATA); /* write */ poke(OUT_DATA,achar); poke(OUT_STATUS,1); while (peek(OUT_STATUS) != 0); }

Interrupt I/O • Busy/wait is very inefficient. • CPU can’t do other work while testing device. • Hard to do simultaneous I/O. • Interrupts allow a device to request CPU attention when it needs. • Interrupt CPU and call new subroutine to handle device • Interrupt Service Routine (ISR) or Interrupt Service Handler.

Generic interrupt mechanism continue execution intr? Assume priority selection is handled before this point. N Y N ignore intr priority > current priority? Y ack Y Y N bus error timeout? vector? Y call table[vector]

Interrupt sequence • CPU acknowledges request. • Device sends vector. • CPU calls handler. • Software processes request. • CPU restores state to foreground program.

Priorities and vectors • Two mechanisms allow us to make interrupts more specific: • Priorities determine what interrupt gets CPU first. • Vectors determine what code is called for each type of interrupt. • Mechanisms are orthogonal: most CPUs provide both.

Interrupt prioritization • Masking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete. • Non-maskable interrupt (NMI): highest-priority, never masked. • Often used for power-down.

Micro-processor System bus 7 Inta 5 Priority arbiter Peripheral1 Peripheral2 Int 3 2 2 Ireq1 Iack1 6 Ireq2 Iack2 Priority arbiter • Single-purpose controller • Peripherals make requests to arbiter, arbiter makes requests to resource • Arbiter connected to system bus for configuration only

P System bus Peripheral1 Peripheral2 Inta Ack_in Ack_out Ack_in Ack_out Int 0 Req_out Req_in Req_out Req_in Daisy-chain aware peripherals Arbitration: Daisy-chain arbitration • Peripherals connected to each other in daisy-chain manner • One peripheral connected to resource, all others connected “upstream” • Peripheral’s req flows “downstream” to resource, resource’s ack flows “upstream” to requesting peripheral • Closest peripheral has highest priority

Arbitration: Daisy-chain arbitration • Pros/cons • Easy to add/remove peripheral - no system redesign needed • Does not support dynamic priority • One broken peripheral can cause loss of access to other peripherals

Interrupt vectors • Allow different devices to be handled by different code. • Interrupt vector table: Interrupt vector table head handler 0 handler 1 handler 2 handler 3

Sources of interrupt overhead • Handler execution time. • Interrupt mechanism overhead. • Register save/restore. • Pipeline-related penalties. • Cache-related penalties.

Direct memory access (DMA) • DMA provides parallelism on bus by controlling transfers without CPU. • Microprocessor could handle this with ISR • Storing and restoring microprocessor state inefficient • Regular program must wait • DMA controller more efficient • Separate single-purpose processor • Microprocessor relinquishes control of system bus to DMA controller • Microprocessor can meanwhile execute its regular program • No inefficient storing and restoring state due to ISR call • Regular program need not wait unless it requires the system bus memory I/O CPU DMA

DMA operation • CPU sets up DMA transfer: • Start address of source/destination. • Length. • Transfer block length. • DMA controller request bus • Processor grants the bus usage • DMA controller performs transfer, signals when done:

Data Transfer Using DMA • Cycle Steal • The DMA controller generates read or write signals at cycles when the processor is not using the bus • Burst Transfer • Transfer a block of data within certain consecutive cycles • CPU may be halted completely.

Device Drivers • What • Provides an interface for the software to communicate with the hardware • Initialization, management, can be used by higher layers of software • Designed to be portable across processor architectures and operating systems • A software layer between hardware and OS • Delivery format • Delivered as source code, allowing it to be built and optimized • Minimized assembly language • C programming language

Typical Functions • Startup • Shutdown • Disable • Enable • Acquire • Release • Read/write • Install/install

Drivers: Level 0 / Level 1 • (Layer 2) RTOS application layer • (Layer 1) High-level device drivers that are full-featured and portable across operating systems and processors • (Layer 0) Low-level drivers for simple use cases

Summary • Program I/O • Interrupt • DMA • Device driver

Hardware/software Interfacing