1 / 77

Digital Electronics Tutorial: Combinational Logic Design Examples Solutions

Digital Electronics Tutorial: Combinational Logic Design Examples Solutions. Problem #1.

josephinekirby
Download Presentation

Digital Electronics Tutorial: Combinational Logic Design Examples Solutions

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Digital ElectronicsTutorial: Combinational Logic Design Examples Solutions ELEC1041 - Combinational Logic Examples - 1

  2. Problem #1 Develop a minimized Boolean implementation of a “ones count” circuit that works as follows. The subsystem has four binary inputs A, B, C, D, and generates a 3-bit output, XYZ. XYZ is 000 if none of the inputs are 1, 001 if one input is 1, 010 if two are one, 011 if three inputs are 1, and 100 if all four inputs are 1. (a)Draw the truth tables for XYZ (A, B, C, D). (b)Minimize the functions X, Y, Z using 4-variable K-maps. Write down the Boolean expressions for the minimized Sum of Products form of each function. (c)Repeat the minimization process, this time deriving Product of Sums form. ELEC1041 - Combinational Logic Examples - 2

  3. Problem #1 Solution (1/6) (a)Draw the truth tables for XYZ (A, B, C, D). ELEC1041 - Combinational Logic Examples - 3

  4. Problem #1 Solution (2/6) (b)Minimize the functions X, Y, Z using 4-variable K-maps. Write down the Boolean expressions for the minimized Sum of Products form of each function. ELEC1041 - Combinational Logic Examples - 4

  5. Problem #1 Solution (3/6) ELEC1041 - Combinational Logic Examples - 5

  6. Problem #1 Solution (4/6) (c)Repeat the minimization process, this time deriving Product of Sums form. ELEC1041 - Combinational Logic Examples - 6

  7. Problem #1 Solution (5/6) ELEC1041 - Combinational Logic Examples - 7

  8. Problem #1 Solution (6/6) ELEC1041 - Combinational Logic Examples - 8

  9. Problem #2 Consider a combinational logic subsystem that performs a two-bit addition function. It has two 2-bit inputs A B and C D, and forms the 3-bit sum X Y Z. (a)Draw the truth tables for XYZ(A,B,C,D). (b)Minimize the functions using 4-variable K-maps to derive minimized Sum of Products forms. (c)In your textbook and in class/lab we have introduced the Full Adder circuit. What is the relative performance to compute the resulting sum bits of the 2-bit adder compared to two full adders connected together? (Hint: which has the worst delay in terms of gates to pass through between the inputs and the final outputs, and how many gates is this?). ELEC1041 - Combinational Logic Examples - 9

  10. Problem #2 Solution (1/3) (a)Draw the truth tables for XYZ(A,B,C,D). • 0 00 • 01 • 10 • 11 ELEC1041 - Combinational Logic Examples - 10

  11. Problem #2 Solution (2/3) (b)Minimize the functions using 4-variable K-maps to derive minimized Sum of Products forms. ELEC1041 - Combinational Logic Examples - 11

  12. Problem #2 Solution (3/3) (c)In your textbook and in class/lab we have introduced the Full Adder circuit. What is the relative performance to compute the resulting sum bits of the 2-bit adder compared to two full adders connected together? (Hint: which has the worst delay in terms of gates to pass through between the inputs and the final outputs, and how many gates is this?). The above circuit is better because there are only two gate levels. But the adder circuit can be used to build adder circuit of more bits. I can’t imagine doing a K-map to construct a adder circuit of 64 bits using the method above. ELEC1041 - Combinational Logic Examples - 12

  13. Problem #3 Show how to implement the full adder Sum(A, B, Cin) and Carry(A, B, Cin) in terms of: (a)Two 8:1 multiplexers; (b)Two 4:1 multiplexers; (c)If you are limited to 2:1 multiplexers (and inverters) only, how would you use them to implement the full adder and how many 2:1 multiplexers would you need? ELEC1041 - Combinational Logic Examples - 13

  14. Ai Bi Cin Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1Ai Bi Cin Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1 Problem #3 Solution (1/8) ELEC1041 - Combinational Logic Examples - 14

  15. Ai Bi Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Ai Bi Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Problem #3 Solution (2/8) (a)Two 8:1 multiplexers (Sum); ELEC1041 - Combinational Logic Examples - 15

  16. Ai Bi Cin Cout0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1Ai Bi Cin Cout0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1 Problem #3 Solution (3/8) (a)Two 8:1 multiplexers (Carry); ELEC1041 - Combinational Logic Examples - 16

  17. Ai Bi Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Ai Bi Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Problem #3 Solution (4/8) (b)Two 4:1 multiplexers (Sum); ELEC1041 - Combinational Logic Examples - 17

  18. Ai Bi Cin Cout0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1Ai Bi Cin Cout0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1 Problem #3 Solution (5/8) (b)Two 4:1 multiplexers (Carry); ELEC1041 - Combinational Logic Examples - 18

  19. Ai Bi Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Ai Bi Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Problem #3 Solution (6/8) (c)2:1 multiplexers (sum) ELEC1041 - Combinational Logic Examples - 19

  20. Ai Bi Cin Cout0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1Ai Bi Cin Cout0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1 Problem #3 Solution (7/8) (c)2:1 multiplexers (Carry) ELEC1041 - Combinational Logic Examples - 20

  21. Ai Bi Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Ai Bi Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Problem #3 Solution (8/8) (c)2:1 multiplexers (Sum) Ver 2 - USE the same carry ELEC1041 - Combinational Logic Examples - 21

  22. Problem #4 Design a combinational logic subsystem with three inputs, I3, I2, I1, and two outputs, O1, O0, that behaves as follows. The outputs indicate the highest index of the inputs that is driven high. For example, if I3 is 0, I2 is 1, I1 is 1, then O1, O0 would be 10 (i.e., I2 is the highest input set to 1). (a)Specify the function by filling out a complete truth table. (b)Develop the minimized gate-level implementation using the K-map method. (c)Develop an implementation using two 4:1 multiplexers. (d)Compare your implementation for (b) and (c). Which is better and under what criterion? ELEC1041 - Combinational Logic Examples - 22

  23. Problem #4 Solution (1/5) (a)Specify the function by filling out a complete truth table. I3 I2 I1 O1 O0 0 0 0 0 0 0 0 1 0 1 0 1 x 1 0 1 x x 1 1 ELEC1041 - Combinational Logic Examples - 23

  24. Problem #4 Solution (2/5) (b)Develop the minimized gate-level implementation using the K-map method. I3 I2 I1 O1 O0 0 0 0 0 0 0 0 1 0 1 0 1 x 1 0 1 x x 1 1 ELEC1041 - Combinational Logic Examples - 24

  25. Problem #4 Solution (3/5) (c)Develop an implementation using two 4:1 multiplexers. I3 I2 I1 O1 O0 0 0 0 0 0 0 0 1 0 1 0 1 x 1 0 1 x x 1 1 ELEC1041 - Combinational Logic Examples - 25

  26. Problem #4 Solution (4/5) (c)Develop an implementation using two 4:1 multiplexers. I3 I2 I1 O1 O0 0 0 0 0 0 0 0 1 0 1 0 1 x 1 0 1 x x 1 1 ELEC1041 - Combinational Logic Examples - 26

  27. Problem #4 Solution (5/5) (d)Compare your implementation for (b) and (c). Which is better and under what criterion? ELEC1041 - Combinational Logic Examples - 27

  28. A B C D W X Y Z S Problem #5 You are to design a simple combinational subsystem to the following specification. The system has the ability to pass its inputs directly to its outputs when a control input, S, is not asserted. It interchanges its inputs when the control input S is asserted. For example, given four inputs A, B, C, D and four outputs W, X, Y, Z, when S=0, WXYZ=ABCD and when S=1, WXYZ=BCDA.  Show how to implement this functionality using building blocks that are restricted to be 2:1 multiplexers and 2:1 demultiplexers. Draw your solution below, using black boxes for the mux/demux blocks. ELEC1041 - Combinational Logic Examples - 28

  29. A W B X C Y D Z S Problem #5 Solution Each output is tied to the output of a 2:1 Multiplexer. S is the select signal. ELEC1041 - Combinational Logic Examples - 29

  30. Problem #6 Your task is to design a combinational logic subsystem to decode a hexadecimal digit in the range of 0 through 9, A through F to drive a seven-segment display. The hexadecimal numerals are as follows:  Design a minimized implementation in PLA form. That is, look for common terms among the seven output functions. ELEC1041 - Combinational Logic Examples - 30

  31. c0 c2 c1 c0 c1 c2 c3 c4 c5 c6 c3 c4 c5 c6 BCD to 7–segmentcontrol signaldecoder A B C D Problem #6 Solution (1/5) ELEC1041 - Combinational Logic Examples - 31

  32. c0 c2 c1 c0 c1 c2 c3 c4 c5 c6 c3 c4 c5 c6 BCD to 7–segmentcontrol signaldecoder A B C D Problem #6 Solution (2/5) ELEC1041 - Combinational Logic Examples - 32

  33. A B C D BCD BCD ACD BCD ABD BCD ACD ABC ABC ABD ABC ABC ABC ABD ABD ACD ACD ABC F0 F1 F2 F3 F4 F5 F6 Problem #6 Solution (3/5) ELEC1041 - Combinational Logic Examples - 33

  34. A B C D BCD BCD ACD BCD ABD BCD ACD ABC ABC ABD ABC ABC ABC ABD ABD ACD ACD ABC F0 F1 F2 F3 F4 F5 F6 Problem #6 Solution (4/5) 18 terms ELEC1041 - Combinational Logic Examples - 34

  35. A B C D ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD F0 F1 F2 F3 F4 F5 F6 Problem #6 Solution (5/5) 16 terms ELEC1041 - Combinational Logic Examples - 35

  36. Problem #7 Calendar subsystem Determine number of days in a month (to control watch display) used in controlling the display of a wrist-watch LCD screen inputs: month, leap year flag outputs: number of days ELEC1041 - Combinational Logic Examples - 36

  37. Problem #7 Solution (1/3) Calendar subsystem Use software implementation to help understand the problem • integer number_of_days ( month, leap_year_flag) { • switch (month) { • case 1: return (31); • case 2: if (leap_year_flag == 1) • then return (29) else return (28); • case 3: return (31); • case 4: return (30); • case 5: return (31); • case 6: return (30); • case 7: return (31); • case 8: return (31); • case 9: return (30); • case 10: return (31); • case 11: return (30); • case 12: return (31); • default: return (0); • } • } ELEC1041 - Combinational Logic Examples - 37

  38. month leap 28 29 30 310000 – – – – –0001 – 0 0 0 10010 0 1 0 0 00010 1 0 1 0 00011 – 0 0 0 10100 – 0 0 1 00101 – 0 0 0 10110 – 0 0 1 00111 – 0 0 0 11000 – 0 0 0 11001 – 0 0 1 01010 – 0 0 0 11011 – 0 0 1 01100 – 0 0 0 11101 – – – – –111– – – – – –month leap 28 29 30 310000 – – – – –0001 – 0 0 0 10010 0 1 0 0 00010 1 0 1 0 00011 – 0 0 0 10100 – 0 0 1 00101 – 0 0 0 10110 – 0 0 1 00111 – 0 0 0 11000 – 0 0 0 11001 – 0 0 1 01010 – 0 0 0 11011 – 0 0 1 01100 – 0 0 0 11101 – – – – –111– – – – – – month leap 28 29 30 31 Problem #7 Solution (2/3) Formalize the problem Encoding: binary number for month: 4 bits 4 wires for 28, 29, 30, and 31one-hot – only one true at any time Block diagram: ELEC1041 - Combinational Logic Examples - 38

  39. month leap 28 29 30 310000 – – – – –0001 – 0 0 0 10010 0 1 0 0 00010 1 0 1 0 00011 – 0 0 0 10100 – 0 0 1 00101 – 0 0 0 10110 – 0 0 1 00111 – 0 0 0 11000 – 0 0 0 11001 – 0 0 1 01010 – 0 0 0 11011 – 0 0 1 01100 – 0 0 0 11101 – – – – –111– – – – – –month leap 28 29 30 310000 – – – – –0001 – 0 0 0 10010 0 1 0 0 00010 1 0 1 0 00011 – 0 0 0 10100 – 0 0 1 00101 – 0 0 0 10110 – 0 0 1 00111 – 0 0 0 11000 – 0 0 0 11001 – 0 0 1 01010 – 0 0 0 11011 – 0 0 1 01100 – 0 0 0 11101 – – – – –111– – – – – – Problem #7 Solution (3/3) Choose implementation target and perform mapping Discrete gates 28 = 29 = 30 = 31 = Can translate to S-o-P or P-o-S m8’ m4’ m2 m1’ leap’ m8’ m4’ m2 m1’ leap m8’ m4 m1’ + m8 m1 m8’ m1 + m8 m1’ ELEC1041 - Combinational Logic Examples - 39

  40. Problem #8 Leap year flag Determine value of leap year flag given the year For years after 1582 (Gregorian calendar reformation), leap years are all the years divisible by 4, except that years divisible by 100 are not leap years, but years divisible by 400 are leap years. ELEC1041 - Combinational Logic Examples - 40

  41. Problem #8 Solution (1/5) Leap year flag Encoding the year: binary – easy for divisible by 4, but difficult for 100 and 400 (not powers of 2) BCD – easy for 100, but more difficult for 4, what about 400? Parts: construct a circuit that determines if the year is divisible by 4 construct a circuit that determines if the year is divisible by 100 construct a circuit that determines if the year is divisible by 400 combine the results of the previous three steps to yield the leap year flag ELEC1041 - Combinational Logic Examples - 41

  42. Problem #8 Solution (2/5) Divisible-by-4 circuit BCD coded year YM8 YM4 YM2 YM1 – YH8 YH4 YH2 YH1 – YT8 YT4 YT2 YT1 – YO8 YO4 YO2 YO1 Only need to look at low-order two digits of the year all years ending in 00, 04, 08, 12, 16, 20, etc. are divisible by 4 if tens digit is even, then divisible by 4 if ones digit is 0, 4, or 8 if tens digit is odd, then divisible by 4 if the ones digit is 2 or 6. Translates into the following Boolean expression (where YT1 is the year's tens digit low-order bit, YO8 is the high-order bit of year's ones digit, etc.): YT1’ (YO8’ YO4’ YO2’ YO1’ + YO8’ YO4 YO2’ YO1’ + YO8 YO4’ YO2’ YO1’ ) + YT1 (YO8’ YO4’ YO2 YO1’ + YO8’ YO4 YO2 YO1’ ) Digits with values of 10 to 15 will never occur, simplify further to yield: YT1’ YO2’ YO1’ + YT1 YO2 YO1’ ELEC1041 - Combinational Logic Examples - 42

  43. Problem #8 Solution (3/5) Divisible-by-100 and divisible-by-400 circuits Divisible-by-100 just requires checking that all bits of two low-order digits are all 0: YT8’ YT4’ YT2’ YT1’ • YO8’ YO4’ YO2’ YO1’ Divisible-by-400 combines the divisible-by-4 (applied to the thousands and hundreds digits) and divisible-by-100 circuits (YM1’ YH2’ YH1’ + YM1 YH2 YH1’) • (YT8’ YT4’ YT2’ YT1’ • YO8’ YO4’ YO2’ YO1’ ) ELEC1041 - Combinational Logic Examples - 43

  44. Problem #8 Solution (4/5) Combining to determine leap year flag Label results of previous three circuits: D4, D100, and D400 leap_year_flag = D4 (D100 • D400’ ) ’ = D4 • D100’ + D4 • D400 = D4 • D100’ + D400 ELEC1041 - Combinational Logic Examples - 44

  45. Problem #8 Solution (5/5) Implementation of leap year flag ELEC1041 - Combinational Logic Examples - 45

  46. Problem #9 Consider the following functions, which are five different functions over the inputs A,B,C,D. (1)F(A,B,C) =åm(1,2,6,7) (2)F(A,B,C,D) =åm(0,1,3,9,11,12,14,15) (3)F’(A,B,C,D) =åm(2,4,5,6,7,8,10,13) (4)F(A,B,C,D) = (A B C + A’ B’) (C + D) (5)    F(A,B,C,D) = (A + B + C) (A + B + C’ + D) (A + B’ + C + D’) (A’ + B’) a) you were to implement these in a single PLA structure with four inputs, five outputs, and an unlimited number of product terms, how many unique product terms are there in this PLA implementation b) If you are trying to maximize the number of shared product terms across the five functions, rather than minimizing the literal count for each function independently, how many unique terms do you obtain? Draw the new K-maps with your selection of implicants that minimizes the number of unique terms across all five functions ELEC1041 - Combinational Logic Examples - 46

  47. Problem #9 Solution (1/2) Consider the following functions, which are five different functions over the inputs A,B,C,D. (1)F(A,B,C) =åm(1,2,6,7) (2)F(A,B,C,D) =åm(0,1,3,9,11,12,14,15) (3)F’(A,B,C,D) =åm(2,4,5,6,7,8,10,13) (4)F(A,B,C,D) = (A B C + A’ B’) (C + D) (5)    F(A,B,C,D) = (A’ + B + C) (A + B + C’ + D) (A + B’ + C + D’) (A’ + B’) a) you were to implement these in a single PLA structure with four inputs, five outputs, and an unlimited number of product terms, how many unique product terms are there in this PLA implementation F(A,B,C)= BC’+AB+A’B’C F(A,B,C,D)=ABD’+ACD+B’D+A’B’C’ F’(A,B,C,D)=A’B+BC’D+AB’D’+B’CD’ F(A,B,C,D)=A’B’D+A’B’C+ABC F(A,B,C,D)=A’C’D’+A’B’D+A’BC+AB’C From Revision Tutorial 17 unique terms ELEC1041 - Combinational Logic Examples - 47

  48. Problem #9 Solution (2/2) b) If you are trying to maximize the number of shared product terms across the five functions, rather than minimizing the literal count for each function independently, how many unique terms do you obtain? Draw the new K-maps with your selection of implicants that minimizes the number of unique terms across all five functions 1. BC’ + AB + A’B’C => ABD' + ABD + A'BC' + ABC' + A'B'C 2. ABD’ + ACD + B’D + A’B’C’ => ABD' + ACD + AB'D + A'B'D + B'CD + B'C'D + A'B'C'  3. A’B + BC’D + AB’D’ + B’CD’ => A'BC + A'BC' + A'BD + A'BD' + BC'D + AB'D' + B'CD' 4. A’B’D + A’B’C + ABC => A’B’D + A’B’C + ABC 5. A’C’D’+A’B’D+A’BC+AB’C => A’C’D’+A’B’D+A’BC+AB’C   shared terms: A'B'C is shared between 1 and 4. A’BC’ is shared between 1 and 3. ABD' is shared between 1 and 2. A’B’D is shared between 2, 4 and 5. A’BC is shared between 3 and 5. 5 shared terms +[22 – (4  2) – (1  3)] => 11 unique terms across all five functions NOTE: PLA Minimization is always carried out by CAD Tools ELEC1041 - Combinational Logic Examples - 48

  49. 0 1 2 3 4 5 6 7 F(A,B,C,D) S2 S1 S0 A B C Problem #10 Consider the following Boolean function in Product of Sums form:  F(A,B,C,D) = (A + B’ + D) (A’ + B’ + D) (B’ + C’ + D’) (A’ + C + D) (A’ + C’ + D)  Show how to implement this function with an 8:1 multiplexer, with A,B,C on the control inputs and D, its complement, and the constants 0 and 1 available as data inputs. Show your work: ELEC1041 - Combinational Logic Examples - 49

  50. 0 1 2 3 4 5 6 7 F(A,B,C,D) S2 S1 S0 A B C Problem #10 Solution (1/2)  F(A,B,C,D) = (A + B’ + D) (A’ + B’ + D) (B’ + C’ + D’) (A’ + C + D) (A’ + C’ + D) ELEC1041 - Combinational Logic Examples - 50

More Related