1 / 8

RD53 IP s

RD53 IP s. Jorgen Christiansen / PH-ESE. IP blocks for RD53. N eed large variety of IP blocks to make our large and complex, high rate pixel chips. They will finally be integrated into “one” final design We need one “perfectly” working version of each vital function.

josiah
Download Presentation

RD53 IP s

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. RD53 IPs Jorgen Christiansen / PH-ESE

  2. IP blocks for RD53 • Need large variety of IP blocks to make our large and complex, high rate pixel chips. • They will finally be integrated into “one” final design • We need one “perfectly” working version of each vital function. • Not many different incomplete versions of the same ! • Radiation hardness is the major issue ! • Redundant developments should be avoided but can in very specific cases be appropriate: • Analog FE ( Not an IP) • Schedule: ~2 years to make IPs to have full pixel array ROC at end of 3 year RD53 program • Who makes what and how: Now • Specs of each IP: Q1 2014 • Viable schematic/layout: Q4 2014 • Prototype submission: Q1 2015 (shared submissions: milestone) • Tested Prototype: Q2 2015 • Radiation qualification: Q3 2015 • (2nd. Prototype) Q3 2015 (shared submissions: milestone) • Final IP: Q4 2015 • A distributed effort across many people and institutes. • Maximize exchange between groups • Design techniques • Tool experience • Radiation hardness design • etc. • Shared use, but each group have their specific “IP rights” to designed blocks (MOU) • Collaborative effort for pixel chips of ATLAS/CMS/CLIC pixel detectors • Other use: Dedicated agreements to be found

  3. What is needed for an IP ? • IP block for integration into large complex mixed signal ASIC • Definition and specification of function, performance and interface • Design and extensive simulation for conformity with defined specifications across PVT corners, mis-match and radiation effects. • Appropriate DRC and verification for use in large pixel chips (e.g. use of layers, power connections, etc.). • Prototyping and characterization • Radiation testing and qualification. • (Synthesis models for basic digital elements) • P&R views, power verification views, etc. • Simulation model of IP for chip simulation and verification (PVT-R, loading, timing parameters, mixed signal model, etc.) • Documentation. • Built in test functions or appropriate scheme to test function when in final chip. • Transfer to common IP block repository. • Support and possible modifications required to optimize its use/integration in final full scale pixel chips. • And probable a few other forgotten points This is a lot more than “just a piece of layout that probably works OK”

  4. Overlap with other WGs • Specification and function: Top and Sim WG • How to make rad hard: Rad WG • IO related blocks: IO WG (not yet started) • Analog • AnalogFE (shaper, discriminator, ADC/TOT, Threshold DAC) • Fully organized by Analog WG • Other analog: Biasing, monitoring ADC, Analog buffers, temp sensor , radiation sensor , etc. • Expertise from Analog WG with coordination/integration from IP WG • Mixed signal • Digital

  5. Common/centralized tasks • Coordination of who makes what: Organization • Checking/verification of specs: Specification reviews: Organization • Definition of how to make IPs: Document and tools setup • Follow up on progress: Organization • Help and support • 65nm tech support IMEC/TSMC/CERN • Informal RD53 help: known RD53 colleague and/or 65nm/RD53 mailing list • Specific IP help and support: Define specific groups/people for this ?. • Radiation effects : Rad WG • Layer use verification, P&R, etc.: Top WG • Simulation models of IP • Digital model • Analogbehavioral model • Mixed signal model • Timing models with back annotation based on loading, slew rate, , • PVT and radiation corners • Power • Other ? • Common MPW submissions • Final IP verification • Release review: Organization • Common IP repository • Database (Cliosoft) • Verification: DRC, LVS, simulation model, P&R view , , • Access control • Tracing of who have gotten what IPs. For what ?. What version ?

  6. Converge on IP commitments Convergence “algorithm”: • First matrix with signs of interest • Institutes are on purpose “overcommitted” • Identify “families” of IPs with high communalities • SLVS driver/receivers, • PLL – DLL • Power • Etc. Possible close collaboration between a few institutes for a family of IPs • IPs that have already been made in 65nm (e.g. in AIDA) or in the process of being finalized • May not yet have been prototyped/tested • May not have been made for 1Grad but can be adapted • Have not reached the “official” IP level • Similar IPs in other technologies ( e.g. 130nm) • Identify possible synergies/sharing with other projects: • Similar IPs needed by other HEP projects • Synergies can work in both directions • Clarify what is required to make an IP. • Re-iterate IP matrix based on feedback to match with available/guessed resources • Let me know if changes in your Interest profile after this meeting • I will come back to each of you to try to converge on a global proposal Today

  7. IP organization • Still need to formally nominate an IP WG convener and IP repository host lab.

More Related