Evolution-enabled reconfigurable computing using field-programmable analog devices

1. Evolution-enabled reconfigurable computing using field-programmable analog devices Adrian Stoica Xin Guo (*) Ricardo S. Zebulum M. I. Ferguson Didier Keymeulen Jet Propulsion Laboratory California Institute of Technology adrian.stoica@jpl.nasa.gov (*) Chromatech, Alameda CA 94501 MAPLD 2002 1

2. A new generation of hardware A third generation hardware in terms of flexibility and fault tolerance Flexibility, fault-tolerance Self-reconfigurable, evolvable + Automated Design +Artificial/Computational Intelligence Reconfigurable 2005 -100nm - BISR, ITRS’99 Fixed HW Generation 1st 3rd 2nd 2

3. Evolvable Hardware (EHW) = Reconfiguration Mechanism + Reconfigurable HW EHW=RH+RM RM RH Mechanisms of transformation search/optimization techniques HW that can change GA + FPGA EHW Electronics MEMS Antennas BioMEMS 3

4. Adaptation New users New functions Faults Mismatches in fabrication Adaptation Environments 4

5. Adaptive Information Processing Adaptation can be at different levels: at architecture level there are polymorphic architectures that optimally re-combine heterogeneous resources, at lower level At device level devices digital (FPGA, reconfigurable DSP), analog and mixed signal (FPAA), NN Polymorphic Architectures Conventional (fixed) Devices (e.g CPUs) Adaptive Devices e.g. FPGA, FPAA, NN, Reconfigurable DSPs 5

6. Evolutionary synthesis and adaptation of electronic circuits Potential electronic designs/implementations compete; the best ones are slightly modified to search for even more suitable solutions Conversion to a circuit description Chromosomes • Evolutionary Algorithm • Search on a population of chromosomes • select the best designs from a population • reproduce with variation • iterate till goal is reached. 1011001101 0111010110 1101101101 Control bitstrings Models of circuits Extrinsic Simulators (e.g., SPICE) Evaluate responses, assess fitness Target response Intrinsic evolution Reconfigurable hardware Circuit response 7

7. SABLES (Stand Alone Board Level Evolvable System) • Motivation: Search for compact, low-power and autonomous Evolvable Hardware systems. • Approach: integrated system-on-a-chip evolvable systems. 8

8. SABLES (Stand Alone Board Level Evolvable System) • FPTA + DSP 9

9. Evolvable Hardware Binary chromosomes used in GAs are a straightforward mapping for downloading circuits onto reconfigurable chips. Each bit of the chromosome determines the state of a switch in the reconfigurable device. 100011….1111 Simplified Cell in Field Programmable Transistor Array 10

10. FPTA • Implementation of an evolution-oriented reconfigurable architecture (EORA) Chip Architecture Cell Schematic 11

11. FPTA Series FPTA1: 12 cells 0.5u feature size(2000) PTA: one cell 0.5u feature size (1998) FPTA2: 64 cells 0.18u feature size (2001) FPTA3: Stacked sensor-analog-digital processing 12

12. FPTA2 • Basic features • Technology: TSMC 0.18u • Area 5mm x 7mm; • 64 cells; • Total of 256 pins; • 96 analog/digital inputs and provide 64 analog/digital outputs; • 16 bits data bus/9 bits address bus control logic; • About 5000 programming bits; • 16 bits data bus/9 bits address bus control logic. 13

13. DSP • Innovative Integration SBC167stand-alone DSP board; • TMS320C6701processor • 16 analog inputs and outputs at 100 kSamples; • 32 Digital I/O at 7.5MHz. • Fits in a box 8” x 8” x 3”. 14

14. Evolution on SABLES • Half-wave rectifier circuit; • Excitation input of 2kHz sine wave of amplitude 2V; • 9% elite percentage; • 70% crossover; • 4% mutation; • 100 individuals population; • 20 seconds experiments 15

15. Evolution on SABLES (Half-wave rectifier) Stimulus-response waveforms during the evaluation of a population in one generation (left) and for 2 individuals in the population (right) 16

16. Evolution on SABLES (Half-wave rectifier) Best individual of generation a) 1, b) 5, c) 50 d) 82 Solution at generation 82 17

17. Evolution on SABLES (Half-wave rectifier) The fitness function as generations progress. 18

18. Evolution on SABLES (Tunable Filters) • Tunable filter circuit circuit; • Excitation input: • e1 = Asin(2f1) + Bsin (2f2) • A and B unknown a priori ; • 9% elite percentage; • 70% crossover; • 4% mutation; • 400 individuals population; • 60 seconds experiments 19

19. Evolution on SABLES (Tunable Filters) Signal/Noise = 10.8dB Input Input Signal/Noise = 4.1dB Signal/Noise = 18.5dB Output Output Signal/Noise = 16.9dB • Filter characteristic: • 10kHz : -2.86dB attenuation • 20kHz : -15.8dB attenuation • Filter characteristic: • 10kHz : -12.5dB attenuation • 20kHz : -4.8dB attenuation 20

20. Reconfigurable Fuzzy Circuits T(x,y) S(x,y) x x AND OR y y • Choose s Evolve circuits for T and S with various values of s • Find most appropriate s for the particular application: • fuzzy control, • automated reasoning, • fuzzy neural networks 21

21. In1 In2 Connectivity for fuzzy circuits evolved on FPTA chip s=100 22

22. Response of evolved T-norm circuits Response of evolved circuit for T100 Response of evolved circuit for S100 Simulated response (). Target characteristic shown with (+). Good approximation! • Illustrates what can be obtained easily by evolution, • with no prior knowledge of circuit, • with no parametric optimization (W/L), • no flexibility in where inputs/outputs are routed • limited to 2 cells It is possible that humans may be able to design better, but: 1. hasn’t been done before 2. is completely automatic design 23

23. Interconnectivity for FPTA-evolved fuzzy circuits s=1 In1 In2 s=100 In1 In2 24

24. Differences in connections between T-norm circuits s=1 Only a few switches produce a change from a T-norm to another. s=100 It is easy to implement adaptive fuzzy systems, which change the operators from one processing stage to the other 25

25. Fuzzy configurable computing • FPTAs are platforms for fuzzy configurable computing in the same way FPGAs are for conventional/digital computing. In an ASIC version the whole processing described by an algorithm is mapped at once in a fixed circuitry, with building blocks corresponding to various stages of the algorithm. • In an FPGA/FPTA implementation, only a part of the algorithm is mapped first in an instance of the processing machine, after which the chip reconfigures itself to become the blueprint for the next step, and so on. Map Defuz Fuz memory Map Defuz Fuz 26

26. Evolution of Analog Circuit Approximations of Complete Fuzzy Systems • Evolve analog circuits that map the Fuzzy surface for a particular control application 27

27. Evolution Using the FPTA Model Figure 5 – Evolved Circuit using SPICE model including 2 FPTA cells for the ball-juggler fuzzy controller. • Evolution on a 128 nodes supercomputer (EHWPACK); • 128 individuals/200 generations; • Two PTA cells: 48 switches; 28

28. Circuit Response against target Fitness Average error: 3.5% Worst error: 13% 29

29. Conclusions • Programmable analog devices and evolutionary algorithms enable: • Reconfigurable analog computing • Automated configuration/circuit synthesis • Adaptive analog computing  30