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HCAL Upgrade Workshop (SLHC, where nothing is certain)

HCAL Upgrade Workshop (SLHC, where nothing is certain). April 2010 Upgrade Week. Timeline/Milestones. The 2012 and 2015 shutdowns quantize things Will discuss HCAL goals for phase 1 upgrades with these times in mind. Towards 2012. Back-end

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HCAL Upgrade Workshop (SLHC, where nothing is certain)

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  1. HCAL Upgrade Workshop(SLHC, where nothing is certain) April 2010 Upgrade Week D. Baden

  2. Timeline/Milestones • The 2012 and 2015 shutdowns quantize things • Will discuss HCAL goals for phase 1 upgrades with these times in mind D. Baden

  3. Towards 2012 • Back-end • Plan to have at least 1 fully loaded uTCA crate of production modules ready • Add fiber splitters on some number of data fibers, run VME and uTCA simultaneously • Spend the 2012 year commissioning the system. • Goal: when we begin installing and commissioning FE electronics (2016?), we want to have a solid BE in place • Note: new FE requires new BE • HF • Install new PMTs? Will depend on… • The need. LHC data will tell us much. • The fix. Do we have a good tube candidate, what about neutrons, aging, etc. R&D underway • HO • Install Ring1 and Ring 2 SiPMs • Using current HCAL electronics of course D. Baden

  4. Towards 2015 • Back-end • Complete installation of uTCA • Abandon the VME infrastructure • We hope to be able to do some of this quasi-statically over time in the proceeding run • Front-end • Install and commission with new back-end electronics, HB and HE • Admittedly ambitious but…. • Current HCAL FE was built in 2002. HTRs were built in 2004. • We have built our upgrade project around these timelines. We are guardedly optimistic and appropriately conservative D. Baden

  5. This Week: FE • Series of talks/discussion, focused almost entirely on front-end issues • Back-end, simulation, software discussed elsewhere • Main issues covered: • QIE10 progress • GBT • FE readout module (RM) design • Some discussion of SiPM but not the main topic • Radiation testing D. Baden

  6. QIE10 • Specifications… • Much already understood but much remains • Some significant changes from QIE8 (current version) D. Baden

  7. QIE10 Status • 1st stage in development, FE amp only, study AMS .35mSiGe bi-CMOS process • Submitted 2/22/10, expect test bench measurement in May • Compare to simulation models, if ok then move forward • Rad testing under way • HCAL spec: 1011 n/cm2 for SEU and 5x1012 n/cm2 for bulk damage • Decision taken at 2010 workshop, goal for full chip submission 2/2011 • FNAL engineer Zimmerman, we do not have all of his time unfortunately. And we will need it. D. Baden

  8. GBT Discussion • TullioGrassi presented our requirements to Magnus and P. Moreira • 160MHz DDR serial input to GBT • 8B/10B data transmission protocol • P. Moreira provided much information, long discussion of GBT capabilities, possibilities, and HCAL needs • GBT plan to have a “complete” prototype in 2010, followed by extensive testing with a production version 2nd half of 2011 • We have much homework to refine our specifications • GBT may also give us a real path towards a more redundant slow controls • If GBT project can meet our needs then we can commit to being a customer • We are concerned about the schedule. They are losing 2 or 3 key people. • Overall this was a very possible discussion. We are optimistic. D. Baden

  9. FE readout module (RM) • Tullio presented our power/cooling requirements and options • Design to 200W/RBX >> current usage 90W • Need a scheme for delivering more power, but cooling is adequate • We want to try to use the Cern MIC DC-DC converter (discussion…) • Chris Tully led a long discussion on the R&D issues • Many issues. Too many for here. • Much dependence of electronics integration with SiPM vendor • Whether we have an “EDU” or an “ODU”, sorry for the jargon • ADC cards are very ambitious, lots of pins. • Much prototyping now Optical Interface Structure FPGA/GBT emulator and transmitter Zecotek “EDU” D. Baden

  10. RM Integration • Development of the RM is largely driven at this stage by component development • SiPM • GBT (and GBT SCA) • QIE10 • LV regulators • It’s important to guide the parameters of these components as they are being developed D. Baden

  11. Front-End R&D, near term • SiPM. R&D towards choosing a vendor • Have a specific R&D with Zecotek (high density) to reduce the response time and characterize lifetime and radiation response • This is our “EDU” • Have a specific R&D to use large area SiPMs (lower pixels but very fast recovery times, adequate for HCAL) • This is more like an ODU and opens up the vendor pool • RM R&D • Work with GBT group • Specify QIE10 inputs and outputs, and functionality in concert with GBT and overall RM design Depth 4 Depth 3 Depth 2 Depth 1 (Layer-0) D. Baden

  12. Summary of Issues/Requirements(Always Evolving) Baden

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