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SLHC RCT Trigger Upgrade: MicroTCA Development Work

This project focuses on the upgrade of the SLHC RCT Trigger system through MicroTCA development work. It includes the development of firmware, testing of different components, and exploring new features like Base-X Ethernet and IPMI interface. The project also involves building a 2x2 test fabric for trigger algorithm research and development.

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SLHC RCT Trigger Upgrade: MicroTCA Development Work

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  1. SLHC Cal Trigger Upgrade • SLHC Regional Calorimeter Trigger • MicroTCA Development Work • T. Gorski, • P. Klabbers • University of Wisconsin • April 28, 2010

  2. MicroTCA Prototype Crate ELMA Enclosure and Backplane NAT MCH uBlade Puma 600W Power Supply

  3. System R&D: RCT FPGA Firmware Environment Block Diagram (SLHC RCT Board) MODULE POWER FPGA Flash SDRAM (Xilinx FPGA) Pwr Ctl & Monitoring BASE-X Ethernet to Fabric A MAC Core Microblaze Processor (Firmware Core) SDRAM Ctrllr (Parallel I/O To other On- Board FPGAs) Controller MezzanineCard (CMC) Config (SPI) Processor Local Bus (PLB) Interface IPMI Trigger I/O Interface (HDL) Simple Asynch. Interface TTC & Trigger Pipeline(HDL) High Speed Links carrying Trigger Data, Clocks (Backplane and Front Panel)

  4. Ethernet R&D: BASE-X Ethernet Development Platform (MicroTCA std) SATA cable running 1000BASE-X Ethernet Performance: Running TCP/IP Stack under Xilkernel— XMT: 4-40 Mbps (traffic) RCV: 15-20 Mbps Virtex-5 FPGAs running Echo server and client under Xilkernel and TCP/IP stack on two modified ML506 evaluation boards

  5. Prototype Card Development (Both Boards in PCB Fab Stage) • Controller Mezzanine Card (CMC) Rev A • AVR32 Microcontroller • IPMI Interface to MicroTCA System • uTCA-SATA Test Card • Base-X Ethernet test bed • CMC Test Carrier

  6. Ethernet R&D: Initial MicroTCA BASE-X Ethernet Test (May/June 2010) PC (Running Iperf Client) ELMA MicroTCA Backplane NAT MCH (BASE-X Switch) (1000BASE-X Ethernet on UTCA Fabric A) (SATA to Fabric A Test Board) (CAT-5 Cable) (SATA Cable) (Network Uplink) BaseT Switch ML506 Board (Iperf server runs on FPGA)

  7. Hardware/Software R&D: Controller Mezzanine Card (CMC) • 55mm x 45 mm module • 84-pin PMC connector to AMC module • Stands 10mm above main board • Services IPMI function for module • Geographical Address • Main module 12V power control • Passes IP address info from IPMI to FPGA • Controls boot mode of FPGA via CPLD on main board • Based on Atmel UC3A1 AVR32 Microcontroller • Runs off of the +3.3V MicroTCA Management Power • Software Development (C code in AVR FLASH) during Summer 2010 • Use uTCA-SATA Test Card as a Mezzanine Carrier

  8. Trigger Algorithm R&D:2x2 Firmware Test Bed • 4 Aux Cards in a 2x2 test fabric • TTC-based timing and link synchronization test bed • Prototype Test Bed for Rocket I/O “Channel Bonding” for latency management • For Testing Trigger Algorithms with Data Sharing • C source code for test pattern generation • RS-232 Hyperterminal interface

  9. Trigger Algorithm R&D: 2x2 Firmware Test Bed Fabric 0 1 Processing Card Level 4X (Passive) Ch 14 & 15, CK2->CK3 (TTC) To BPCK1, Slots 0-3 3X 4x4 Switches 125 MHz OSC 4X 4X 4X 4X 2 3 Input Card Level 4X

  10. SLHC RCT MicroTCA Activity Summary • 10-Slot MicroTCA Crate now in lab • CMC and uTCA-SATA test boards in PCB fabrication • For building IPMI and embedded Base-X Ethernet capabilities into MicroTCA boards • Learning how NAT-MCH supports these functions • Developing expertise writing TCP/IP server applications to run in FPGA (e.g., HAL, JTAG) • 2x2 Test Fabric constructed using 4 Aux cards and a test fixture PCB • System synchronization and link data alignment work—Channel Bonding • Test bed for multi-FGPA Trigger Algorithm firmware development • Lessons learned in near-term activities to be put to work on SLHC RCT Trigger Prototype boards later in 2010

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