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TCSS 372A Computer Architecture

TCSS 372A Computer Architecture. Getting Started. Get acquainted (take pictures) Discuss purpose, scope, and expectations of the course Discuss personal expectations & strategy for doing well Review Web Page (http://faculty.washington.edu/lcrum)

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TCSS 372A Computer Architecture

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  1. TCSS 372A Computer Architecture

  2. Getting Started • Get acquainted (take pictures) • Discuss purpose, scope, and expectations of the course • Discuss personal expectations & strategy for doing well • Review Web Page (http://faculty.washington.edu/lcrum) • Review Syllabus, Textbook, and Simulator book • Discuss Laboratory (CP 206D), Access, Etiquette, Equipment Check-out • Discuss Homework Format • Laboratory Report Format

  3. CSS 372 - Lecture 1 • Chapter 3 – Connecting Computer Components with Buses • Bus Structures • Synchronous, Asynchronous • Typical Bus Signals • Two level, Tri-state, Wired Or • Hierarchical Bus Organizations • PCI Bus Example

  4. What is a Bus? • A communication pathway connecting two or more devices (Computers, Components, I/O, …) • Usually broadcast • Often grouped • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown

  5. What do Buses look like? • Parallel lines on circuit boards • Ribbon cables • Strip connectors on mother boards • Sets of wires

  6. Physical Realization of Bus Architecture

  7. Communication with Memory via a Bus

  8. Communication with I/O via a Bus

  9. CPU Communication via a Bus

  10. Data Bus (Subset of Bus) • Carries data • Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance • 8, 16, 32, 64 bit

  11. Address Bus (Subset of Bus) • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system • e.g. 8080 has 16 bit address bus giving 64k address space

  12. Control Bus (Subset of Bus) • Control and timing information • Memory read/write signal(s) • Interrupt request/acknowledge signal(s) • Clock signal(s) • Etc.

  13. Power/Ground (Subset of bus ?) • Provides Power and Reference Levels for Devices • May be several voltage levels • Ground may be dispersed between signals

  14. Types of Buses • Dedicated • - Separate data & address lines • Multiplexed • - Shared lines • - Address valid or data valid control line • - Advantage - fewer lines • - Disadvantages • More complex control • Ultimate performance • Synchronous • Asynchronous (Hand Shaking) • Serial (Twisted pair, Coaxial Cable, ..) • Parallel (Ribbon Cable, Bundle of Wires,…)

  15. Physical Considerations for Buses • Media (voltage, optic) • Signal levels – the higher, the more immune to noise • Noise Absorption – wires can pick up noise from neighboring wires • Noise Generation – wires can be antennas • Length Creates Delay ( reduces Bandwidth) Consumes Power Creates reflections – (Terminations become more critical)

  16. Logic Threshold Voltage Levels

  17. Signal Scheme Alternatives • Totempole - High or Low output level Line always at a 1 level or 0 level • Open collector, open drain, wired-or Line is nominally at a 1 level or 0 level – line is “pulled” to non-nominal level • Tristate Has third state – open • Differential Uses a pair of lines – the level is the difference of signals on the two lines.

  18. Bus Challenges • Lots of devices on one bus leads to: • Propagation delays • Long data paths mean that co-ordination of bus use can adversely affect performance • Traffic congestion • Too many devices communicating reduces bandwidth • Alternative - Systems use multiple buses

  19. Simple Computer Bus + clock(s), power(s), and ground(s) Notes: 1) Bus lines need to be properly terminated 2) Power lines are to furnish reference voltage, not power

  20. Adding an Expansion Bus

  21. Hierarchical Bus Structure

  22. Bus Arbitration • More than one module may need to control the bus e.g. CPUs and DMA controller • Only one module may control the bus at one time • Arbitration may be centralised or distributed

  23. Centralised or Distributed Arbitration • Centralised • Single hardware device controlling bus access • Bus Controller • Arbiter • May be part of CPU or separate • Distributed • More than one module may claim the bus Need control logic on all these modules

  24. Timing • Co-ordination of events on bus • Synchronous • Events determined by clock cycles • Control Bus includes clock line(s) • A single 1- 0 sequence is a bus cycle (or phase) • All devices can read clock line • Likely they sync on leading edge • Likely a single cycle for an event (may be multiple clock cycles or phases)

  25. Timing Diagram Conventions

  26. Synchronous Timing Diagram

  27. Asynchronous Timing – Read Diagram

  28. Asynchronous Timing – Write Diagram

  29. Example - PCI Bus • Peripheral Component Interconnection • Intel released to public domain • 32 or 64 bit • 50 lines

  30. Typical PCI Bus Usage

  31. Multiple PCI Bus Configuration

  32. PCI Commands • Transaction between initiator (master) and target • Master claims bus • Determine type of transaction • e.g. I/O read/write • Address phase • One or more data phases

  33. PCI Read Timing Diagram

  34. PCI Bus Arbiter

  35. PCI Bus Arbitration Timing

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