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On-Chip Interconnects Alexander Grubb Jennifer Tam Jiri Simsa Harsha Simhadri

On-Chip Interconnects Alexander Grubb Jennifer Tam Jiri Simsa Harsha Simhadri. Martha Mercaldi Kim, John D. Davis, Mark Oskin, and Todd Austin. “Polymorphic On- Chip Networks,” in Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA) , June 2008.

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On-Chip Interconnects Alexander Grubb Jennifer Tam Jiri Simsa Harsha Simhadri

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  1. On-Chip InterconnectsAlexander GrubbJennifer TamJiri SimsaHarsha Simhadri Martha Mercaldi Kim, John D. Davis, Mark Oskin, and Todd Austin. “Polymorphic On- Chip Networks,” in Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA), June 2008. Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, and Chita R. Das. “MIRA: A Multi-layer On Chip Interconnect Router Architecture,” in Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA), June 2008.

  2. As more processors are put on chip, it is important to have communication infrastructure, interconnect, stay on chip too. Motivation

  3. No single network topology optimal for all workloads. • Are these good workloads to be examining? Motivation

  4. Definition Polymorphic on-chip network - a network which can act like any other network Since polymorphic network can imitate any network by configuring network building blocks, we just need to decide before runtime which network we want to imitate.

  5. Two network components: buffers and connections • Router is just buffers with some logic Polymorphic design

  6. Polymorphic Overhead • ~40% space overhead used for network • How much latency does this extra space introduce? • Could a fixed network be made faster/wider?

  7. Bad traffic models • Time overheads, would simulations outputs remain the same Issues

  8. MIRAMulti-layered On-Chip Interconnect Router Multi-layer connect Multi-layer interconnect Newer fab processes allows multi-layer interconnects You can stack a 128-bit line in to 4x32-bit lateys for lesser power, lesser latency and higher speed Can use this technology to design networks for chips. Main issue: power dissipation

  9. MIRA • Interconnect design elements: • Interconnect buffer • Crossbar • Inter-router link • Routing logic • Switch logic

  10. MIRA • Design considerations • LSBs (and other control signals) change faster than MSBs (which are usually mostly 0s) • Put them on top to dissipate power faster • Interconnect buffer

  11. MIRA • Overall area prop. to width2 • Saves overall area too. • Crossbar: 5x5 ports. Logic controls data flow.

  12. MIRA • Typical Design • 36 nodes. Interconnect is a torus • 8 nodes are cores, 28 are L2 caches. • Used the saved footprint to build multi hop links • Reduces latency • Also saves power as fewer switching in involved

  13. MIRA • Questions • How many layers? • Tradeoffs: heat dissipation, cost Vs latency, total power consumption • What if you could put nodes themselves in multiple layers? • Where would you place the cores and L2 caches • What topology would you implement?

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